SimPL: An effective placement algorithm

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 1, 2012, Pages 50-60

  Kim, Myung Chul ^a   Lee, Dong Jin ^a   Markov, Igor L ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Algorithms; layout; multicore; optimization; physical design; placement

Indexed keywords

BENCHMARK SUITES; EMPIRICAL STUDIES; LAYOUT; LOOK-AHEAD; MULTI CORE; PHYSICAL DESIGN; PLACEMENT; PLACEMENT ALGORITHM; RUNTIMES; SOLUTION QUALITY; WIRE LENGTH;

BENCHMARKING; OPTIMIZATION; PLACERS;

ALGORITHMS;

EID: 84255204462     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2170567     Document Type: Article

References (31)

1. S. N. Adya and I. L. Markov. (2005). Executable Placement Utilities [Online]. Available: http://vlsicad.eecs.umich.edu/BK/PlaceUtils
2. C. J. Alpert, G.-J. Nam, and P. G. Villarrubia, "Effective free space management for cut-based placement via analytical constraint generation," IEEE Trans. Comput.-Aided Des., vol. 22, no. 10, pp. 1343-1353, Oct. 2003.
3. C. J. Alpert, S. K. Karandikar, Z. Li, G.-J. Nam, S. T. Quay, H. Ren, C. N. Sze, P. G. Villarrubia, and M. C. Yildiz, "Techniques for fast physical synthesis," Proc. IEEE, vol. 95, no. 3, pp. 573-599, Mar. 2007.
4. U. Brenner, M. Struzyna, and J. Vygen, "BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms," IEEE Trans. Comput.-Aided Des., vol. 27, no. 9, pp. 1607-1620, Sep. 2008.
5. N. Buchbinder and J. Naor, The Design of Competitive Online Algorithms Via a Primal-Dual Approach. Hanover, MA: NOW Publishers, 2009.
6. A. E. Caldwell, A. B. Kahng, and I. L. Markov, "Can recursive bisection alone produce routable placements?" in Proc. DAC, 2000, pp. 477-482.
7. T. F. Chan, J. Cong, J. R. Shinnerl, K. Sze, and M. Xie, "mPL6: Enhanced multilevel mixed-size placement," in Proc. ISPD, 2006, pp. 212-214. (Pubitemid 44063427)
8. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "NTUPlace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints," IEEE Trans. Comput.-Aided Des., vol. 27, no. 7, pp. 1228-1240, Jul. 2008.
9. J. Cong, M. Romesis, and J. R. Shinnerl, "Fast floorplanning by lookahead enabled recursive bipartitioning," IEEE Trans. Comput.-Aided Des., vol. 25, no. 9, pp. 1719-1732, Sep. 2006. (Pubitemid 44304101)
10. G. Goumas, K. Kourtis, N. Anastopoulos, V. Karakasis, and N. Koziris, "Understanding the performance of sparse matrix-vector multiplication, " in Proc. Euromicro Int. Conf. PDP, Feb. 2008, pp. 283-292.
11. L. Dagum and R. Menon, "OpenMP: An industry standard API for shared-memory programming," IEEE Computat. Sci. Eng., vol. 5, no. 1, pp. 46-55, Jan.-Mar. 1998.
12. M. Garland, "Sparse matrix computations on manycore GPU's," in Proc. DAC, 2010, pp. 2-6.
13. L. Hsu, R. Iyer, S. Makineni, S. Reinhardt, and D. Newell, "Exploring the cache design space for large scale CMPs," ACM SIGARCH Comput. Architect. News, vol. 33, no. 4, pp. 24-33, Nov. 2005.
14. B. Hu and M. Marek-Sadowska, "FAR: Fixed-points addition and relaxation based placement," in Proc. ISPD, 2005, pp. 161-166.
15. D. A. Jamsek, "Designing and optimizing compute kernels on NVIDIA GPUs," in Proc. ASPDAC, 2009, pp. 224-229.
16. A. B. Kahng and Q. Wang, "A faster implementation of APlace," in Proc. ISPD, 2006, pp. 218-220. (Pubitemid 44059921)
17. A. B. Kahng, J. Lienig, I. L. Markov, and J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure. New York: Springer, 2011, pp. 1-312.
18. A. A. Kennings and K. Vorwerk, "Force-directed methods for generic placement," IEEE Trans. Comput.-Aided Des., vol. 25, no. 10, pp. 2076-2087, Oct. 2006. (Pubitemid 44321569)
19. K. Madduri, D. A. Bader, J. W. Berry, and J. R. Crobak, "Parallel shortest path algorithms for solving large-scale instances," in Proc. 9th DIMACS Implementat. Challenge: The Shortest Path Problem, Nov. 2006, pp. 249-290.
20. G.-J. Nam, S. Reda, C. J. Alpert, P. G. Villarrubia, and A. B. Kahng, "A fast hierarchical quadratic placement algorithm," IEEE Trans. Comput.-Aided Des., vol. 25, no. 4, pp. 678-691, Apr. 2006.
21. G.-J. Nam and J. Cong, Modern Circuit Placement: Best Practices and Results. New York: Springer, 2007.
22. M. Pan, N. Viswanathan, and C. Chu, "An efficient and effective detailed placement algorithm," in Proc. ICCAD, 2005, pp. 48-55. (Pubitemid 44815697)
23. S. K. Raman, V. Pentkovski, and J. Keshava, "Implementing streaming SIMD extensions on the Pentium III processor," IEEE Micro, vol. 20, no. 4, pp. 47-57, Jul.-Aug. 2000.
24. J. A. Roy and I. L. Markov, "ECO-system: Embracing the change in placement," IEEE Trans. Comput.-Aided Des., vol. 26, no. 12, pp. 2173-2185, Dec. 2007. (Pubitemid 350157858)
25. J. A. Roy, D. A. Papa, S. N. Adya, H. H. Chan, A. N. Ng, J. F. Lu, and I. L. Markov, "Capo: Robust and scalable open-source min-cut floorplacer," in Proc. ISPD, 2005, pp. 224-226. (Pubitemid 41816870)
26. Y. Saad, Iterative Methods for Sparse Linear Systems. Philadelphia, PA: SIAM, 2003.
27. P. Spindler, U. Schlichtmann, and F. M. Johannes, "Kraftwerk2: A fast force-directed quadratic placement approach using an accurate net model," IEEE Trans. Comput.-Aided Des., vol. 27, no. 8, pp. 1398-1411, Aug. 2008.
28. L. N. Trefethen and D. Bau, Numerical Linear Algebra. Philadelphia, PA: SIAM, 1997, pp. 296-298.
29. N. Viswanathan, M. Pan, and C. Chu, "FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control," in Proc. ASPDAC, 2007, pp. 135-140.
30. N. Viswanathan, G.-J. Nam, C. J. Alpert, P. Villarrubia, H. Ren, and C. Chu, "RQL: Global placement via relaxed quadratic spreading and linearization," in Proc. DAC, 2007, pp. 453-458. (Pubitemid 47130009)
31. S. J. Wright, Primal-Dual Interior-Point Methods. Philadelphia, PA: SIAM, 1987, pp. 1-309.