Capo: Robust and scalable open-source min-cut floorplacer

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2005, Pages 224-226

  Roy, Jarrod A ^a   Papa, David A ^a   Adya, Saurabh N ^a,b   Chan, Hayward H ^a   Ng, Aaron N ^a   Lu, James F ^a   Markov, Igor L ^a  

^a University of Michigan   (United States)

^b Synplicity Inc   (United States)

Author keywords

Floorplanning; Physical Design; Placement

Indexed keywords

FLOORPLANNING; PHYSICAL DESIGN; PLACEMENT;

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; RESEARCH AND DEVELOPMENT MANAGEMENT;

COMPUTER AIDED SOFTWARE ENGINEERING;

EID: 29144503209     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. S. N. Adya, I. L. Markov, P. G. Villarrubia, "On Whitespace and Stability in Mixed-size Placement and Physical Synthesis," ICCAD 2003, pp. 311-318.
2. S. N. Adya et al., "Benchmarking for Large-Scale Placement and Beyond," IEEE Trans. on CAD 23(4), pp. 472-488, 2004.
3. S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, I. L. Markov,"Unification of Partitioning, Placement and Floorplanning," ICCAD, 2004, pp. 550-557.
4. S. N. Adya and I. L. Markov, "Combinatorial Techniques for Mixed-size Placement," ACM Trans. on Design Autom. of Elec. Sys., 10(5), Jan 2005, pp. 58-90. Also see
5. ISPD 2002, pp. 12-17.
6. A. Agnihotri et al., "Fractional Cut: Improved recursive bisection placement," ICCAD, 2003, pp. 307-310.
7. C. J. Alpert, G.-J. Nam, P. G. Villarrubia, "Free-Space Management for Cut-Based Placement," ICCAD 2002, p. 746.
8. U. Brenner and J. Vygen, "Faster Optimal Single-Row Placement with Fixed Ordering," DATE 2000, pp. 117-121.
9. A. E. Caldwell, A. B. Kahng, I. L. Markov, "Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning," ACM J. on Experimental Algorithms, vol. 5, 2000.
10. A. E. Caldwell, A. B. Kahng, I. L. Markov, "Improved Algorithms for Hypergraph Bipartitioning," ASPDAC 2000, pp. 661-666.
11. A. E. Caldwell, A. B. Kahng, I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?" DAC'00, p. 477.
12. A. E. Caldwell, A. B. Kahng, I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout," IEEE Trans. on CAD 19(11), pp. 1304-1314, 2000.
13. A. E. Caldwell, A. B. Kahng, I. L. Markov, "VLSI CAD Bookshelf" http://vlsicad.eecs.umich.edu/BK.
14. Also see A. E. Caldwell, A. B. Kahng, l. L. Markov, "Toward CAD-IP Reuse: The MARCO GSRC Bookshelf of Fundamental CAD Algorithms," IEEE Design and Test, May 2002, pp. 72-81.
15. A. E. Caldwell, A. B. Kahng, I. L. Markov, "Hierarchical Whitespace Allocation in Top-down Placement," IEEE Transactions on CAD 22(11), Nov, 2003, pp. 716-724.
16. A. B. Kahng and S. Reda, "Placement Feedback: A Concept and Method for Better Min-cut Placement," DAC 2004, pp. 357-362.
17. D. A. Papa, S. N. Adya, I. L. Markov, "Constructive Benchmarking for Placement," GLSVLSI 2004, pp. 113-118. http://vlsicad.eecs.umich.edu/BK/FEATURE/
18. N. Selvakkumaran and G. Karypis, "THETO: A Fast and High-Quality Partitioning Driven Global Placer," Technical Report 03-046, 2003, University of Minnesota.
19. X. Tang, R. Tian, M. D.F. Wong, "Optimal Redistribution of White Space for Wire Length Minimization," ASPDAC 2005, p. 412.
20. X. Yang, B.-K. Choi, M. Sarrafzadeh, "Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement," ISPD 2002, pp. 42-50.