An integrated nonlinear placement framework with congestion and porosity aware buffer planning

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 702-707

  Chen, Tung Chieh ^a   Chakraborty, Ashutosh ^b   Pan, David Z ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b The University of Texas at Austin   (United States)

Author keywords

Buffer; Physical design; Placement; VLSI

Indexed keywords

BUFFER; BUFFER PLANNING; PHYSICAL DESIGN; PLACEMENT; VLSI;

CELLS; COMPUTER AIDED DESIGN; COMPUTER NETWORKS; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; POROSITY;

BUFFER CIRCUITS;

EID: 51549090631     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555910     Document Type: Conference Paper

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