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Volumn , Issue , 2010, Pages 568-573

A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance

Author keywords

[No Author keywords available]

Indexed keywords

CELL DENSITY; EQUAL SIZES; MERGING PROCEDURE; RUNTIMES; SPEED-UPS; STANDARD CELL; STANDARD CELL DESIGN; STATE-OF-THE-ART METHODS; WEIGHTED SUM;

EID: 77951230474     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2010.5419819     Document Type: Conference Paper
Times cited : (13)

References (15)
  • 1
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    • Important placement considerations for modern vlsi chips
    • Paul Villarrubia. Important placement considerations for modern vlsi chips. In Proc. ISPD, pages 6-6, 2003.
    • (2003) Proc. ISPD , pp. 6-6
    • Villarrubia, P.1
  • 2
    • 2942673331 scopus 로고    scopus 로고
    • Optimization of linear placements for wirelength minimization with free sites
    • Andrew B. Kahng, Paul Tucker, and Alex Zelikovsky. Optimization of linear placements for wirelength minimization with free sites. In Proc. ASPDAC, pages 241-244, 1999.
    • (1999) Proc. ASPDAC , pp. 241-244
    • Kahng, A.B.1    Tucker, P.2    Zelikovsky, A.3
  • 3
    • 54549117207 scopus 로고    scopus 로고
    • Faster optimal single-row placement with fixed ordering
    • Ulrich Brenner and Jens Vygen. Faster optimal single-row placement with fixed ordering. In Proc. DATE, pages 117-121, 2000.
    • (2000) Proc. DATE , pp. 117-121
    • Brenner, U.1    Vygen, J.2
  • 6
    • 2942630783 scopus 로고    scopus 로고
    • Almost optimum placement legalization by minimum cost flow and dynamic programming
    • Ulrich Brenner, Anna Pauli, and Jens Vygen. Almost optimum placement legalization by minimum cost flow and dynamic programming. In Proc. ISPD, pages 2-9, 2004.
    • (2004) Proc. ISPD , pp. 2-9
    • Brenner, U.1    Pauli, A.2    Vygen, J.3
  • 7
    • 33751414789 scopus 로고    scopus 로고
    • Computational geometry based placement migration
    • Tao Luo, Haoxing Ren, Charles J. Alpert, and David Z. Pan. Computational geometry based placement migration. In Proc. ICCAD, pages 41-47.
    • Proc. ICCAD , pp. 41-47
    • Luo, T.1    Ren, H.2    Alpert, C.J.3    Pan, D.Z.4
  • 9
    • 2942660384 scopus 로고    scopus 로고
    • Method and system for high speed detailed placement of cells within an integrated circuit design
    • U.S. Patent 6370673, April
    • Dwight Hill. Method and system for high speed detailed placement of cells within an integrated circuit design. U.S. Patent 6370673, April 2002.
    • (2002)
    • Hill, D.1
  • 10
    • 43349095254 scopus 로고    scopus 로고
    • Abacus: Fast legalization of standard cell circuits with minimal movement
    • Peter Spindler, Ulf Schlichtmann, and Frank M. Johannes. Abacus: Fast legalization of standard cell circuits with minimal movement. In Proc. ISPD, pages 47-53.
    • Proc. ISPD , pp. 47-53
    • Spindler, P.1    Schlichtmann, U.2    Johannes, F.M.3
  • 11
    • 33745967691 scopus 로고    scopus 로고
    • Architecture and details of high quality large-scale analytical placer
    • Andrew B. Kahng, Sherief Reda, and Qinke Wang. Architecture and details of high quality large-scale analytical placer. In Proc. ASPDAC, pages 890-897, 2005.
    • (2005) Proc. ASPDAC , pp. 890-897
    • Kahng, A.B.1    Reda, S.2    Wang, Q.3
  • 12
    • 49549110217 scopus 로고    scopus 로고
    • Dplace2.0: A stable and efficient analytical placement based on diffusion
    • Tao Luo and David Z. Pan. Dplace2.0: A stable and efficient analytical placement based on diffusion. In Proc. ASPDAC, pages 346-351, 2008.
    • (2008) Proc. ASPDAC , pp. 346-351
    • Luo, T.1    Pan, D.Z.2
  • 13
    • 45849140142 scopus 로고    scopus 로고
    • Ntuplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints
    • July
    • Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, and Yao-Wen Chang. Ntuplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 27(7):1228-1240, July 2008.
    • (2008) IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , vol.27 , Issue.7 , pp. 1228-1240
    • Chen, T.-C.1    Jiang, Z.-W.2    Hsu, T.-C.3    Chen, H.-C.4    Chang, Y.-W.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.