Towards layout-friendly high-level synthesis

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2012, Pages 165-172

  Cong, Jason ^a,b   Liu, Bin ^a   Luo, Guojie ^a,b   Prabhakar, Raghu ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b PEKING UNIVERSITY   (China)

Author keywords

High level synthesis; Interconnect estimation; Routability

Indexed keywords

ABSTRACTION LEVEL; DESIGN COMPLEXITY; DESIGN DECISIONS; HIGH LEVEL SYNTHESIS; INTERCONNECT DESIGN; INTERCONNECT ESTIMATION; LAYOUT-FRIENDLY; ROUTABILITY; STRUCTURAL METRICS; TECHNOLOGY SCALING;

DESIGN;

PROBLEM SOLVING;

EID: 84860231365     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2160916.2160952     Document Type: Conference Paper

References (40)

1. Altera Quartus II. Available: http://www.altera.com.
2. Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Release 70731. Available: http://www.eecs.berkeley.edu/~alanmi/abc/.
3. VPR and T-VPack 5.0.2. Available: http://www.eecg.toronto.edu/vpr/.
4. V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999.
5. S. Boyd and L. Vandenberghe. Convex Optimization. Cambridge University Press, New York, NY, 2004.
6. L. Carloni, K. McMillan, and A. Sangiovanni-Vincentelli. Theory of latency-insensitive design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 20(9):1059{1076, Sept. 2001. (Pubitemid 32945718)
7. D. Chen and J. Cong. Register binding and port assignment for multiplexer optimization. In Proc. Asia and South Pacific Design Automation Conf., pages 68{73, 2004.
8. C.-L. E. Cheng. Risa: accurate end efficient placement routability modeling. In Proc. Int. Conf. on Computer-Aided Design, pages 690{695, Nov. 1994.
9. J. Cong. An interconnect-centric design ow for nanometer technologies. Proc. IEEE, 89(4):505{528, 2001.
10. J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang. Platform-based behavior-level and system-level synthesis. In Proc. IEEE Int. SOC Conf., pages 199{202, 2006. (Pubitemid 351688708)
11. J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang. Architecture and synthesis for on-chip multicycle communication. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 23(4):550{564, April 2004.
12. J. Cong, Y. Fan, and W. Jiang. Platform-based resource binding using a distributed register-file microarchitecture. In Proc. Int. Conf. on Computer-Aided Design, pages 709{715, 2006.
13. J. Cong, W. Jiang, B. Liu, and Y. Zou. Automatic memory partitioning and scheduling for throughput and power optimization. In Proc. Int. Conf. on Computer-Aided Design, pages 697{704, 2009.
14. J. Cong and B. Liu. A metric for layout-friendly microarchitecture optimization in high-level synthesis. In Proc. Design Automation Conf., 2012. in press.
15. J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K. Vissers, and Z. Zhang. High-level synthesis for FPGAs: From prototyping to deployment. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 30(4):473{491, Apr. 2011.
16. J. Cong, B. Liu, and J. Xu. Coordinated resource optimization in behavioral synthesis. In Proc. Design, Automation and Test in Europe, pages 1267{1272, 2010.
17. J. Cong and Z. Zhang. An efficient and versatile scheduling algorithm based on SDC formulation. In Proc. Design Automation Conf., pages 433{438, 2006. (Pubitemid 47113937)
18. W. Dougherty and D. Thomas. Unifying behavioral synthesis and physical design. In Proc. Design Automation Conf., pages 756{761, 2000.
19. C. Dubach, T. M. Jones, E. V. Bonilla, G. Fursin, and M. F. P. O'Boyle. Portable compiler optimisation across embedded programs and microarchitectures using machine learning. In Proc. Int. Symp. on Microarchitecture, pages 78{88, 2009.
20. Y.-M. Fang and D. F. Wong. Simultaneous functional-unit binding and oorplanning. In Proc. Int. Conf. on Computer-Aided Design, pages 317{321, 1994.
21. R. Gupta and F. Brewer. High-Level Synthesis: A Retrospective, pages 13{28. Springer, 2008.
22. C.-Y. Huang, Y.-S. Chen, Y.-L. Lin, and Y.-C. Hsu. Data path allocation based on bipartite weighted matching. In Proc. Design Automation Conf., pages 499{504, 1990.
23. T. Kim and X. Liu. Compatibility path based binding algorithm for interconnect reduction in high level synthesis. In Proc. Int. Conf. on Computer-Aided Design, pages 435{441, 2007.
24. P. Kudva, A. Sullivan, and W. Dougherty. Measurements for structural logic synthesis optimizations. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 22(6):665{674, June 2003.
25. T. Kutzschebauch and L. Stok. Congestion aware layout driven logic synthesis. In Proc. Int. Conf. on Computer-Aided Design, pages 216{223, 2001. (Pubitemid 33148961)
26. C. Li, M. Xie, C.-K. Koh, J. Cong, and P. Madden. Routability-driven placement and white space allocation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 26(5):858{871, May 2007. (Pubitemid 46748271)
27. S. Liu, K.-R. Pan, M. Pedram, and A. Despain. Alleviating routing congestion by combining logic resynthesis and linear placement. In Proc. European Conf. on Design Automation, pages 578{582, Feb. 1993.
28. S. Mayrhofer and U. Lauther. Congestion-driven placement using a new multi-partitioning heuristic. In Proc. Int. Conf. on Computer-Aided Design, pages 332{335, Nov. 1990. (Pubitemid 21675437)
29. M. C. McFarland. Reevaluating the design space for register transfer hardware synthesis. In Proc. Int. Conf. on Computer-Aided Design, pages 262{265, 1987.
30. L. McMurchie and C. Ebeling. PathFinder: a negotiation-based performance-driven router for FPGAs. In Proc. Int. Symp. on FPGA, pages 111{117, 1995.
31. D. Pandini, L. Pileggi, and A. Strojwas. Congestion-aware logic synthesis. In Proc. Design, Automation and Test in Europe, pages 664{671, 2002.
32. B. M. Pangre. Splicer: a heuristic approach to connectivity binding. In Proc. Design Automation Conf., pages 536{541, 1988.
33. S. Posluszny, N. Aoki, D. Boerstler, P. Coulman, S. Dhong, B. Flachs, P. Hofstee, N. Kojima, O. Kwon, K. Lee, D. Meltzer, K. Nowka, J. Park, J. Peter, J. Silberman, O. Takahashi, and P. Villarrubial. \Timing closure by design," a high frequency microprocessor design methodology. In Proc. Design Automation Conf., pages 712{717, 2000.
34. J. Roy, S. Adya, D. Papa, and I. Markov. Min-cut oorplacement. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 25(7):1313{1326, July 2006.
35. P. Saxena, R. S. Shelar, and S. S. Sapatnekar. Routing Congestion in VLSI Circuits: Estimation and Optimization. Springer, 2007.
36. M. Stephenson, S. Amarasinghe, M. Martin, and U.-M. O'Reilly. Meta optimization: improving compiler heuristics with machine learning. In Proc. ACM SIGPLAN Conf. on Programming Language Design and Implementation, pages 77{90, 2003.
37. S. Tarafdar, M. Leeser, and Z. Yin. Integrating oorplanning in data-transfer based high-level synthesis. In Proc. Int. Conf. on Computer-Aided Design, pages 412{417, 1998.
38. L. Vandenberghe and S. Boyd. Semidefinite programming. SIAM Review, 38(1):49{95, 1996. (Pubitemid 126610912)
39. J.-P. Weng and A. C. Parker. 3D scheduling: high-level synthesis with oorplanning. In Proc. Design Automation Conf., pages 668{673, 1991.
40. M. Xu and F. J. Kurdahi. Layout-driven RTL binding techniques for high-level synthesis using accurate estimators. ACM Trans. on Design Automation of Electronics Systems, 2:312{343, Oct. 1997 (Pubitemid 127759528)