Obstacle-aware clock-tree shaping during placement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 2, 2012, Pages 205-216

  Lee, Dong Jin ^a   Markov, Igor L ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Algorithms; clock network synthesis; low power; optimization; physical design; placement

Indexed keywords

CLOCK NETWORK; CLOCK NETWORK SYNTHESIS; CLOCK ROUTING; CLOCK TREE; CLOCK-TREE SYNTHESIS; CONTRACTION FORCE; DYNAMIC POWER CONSUMPTION; GATED CLOCKS; INTEGRATED CIRCUIT DESIGNS; LOW POWER; MACRO BLOCK; MULTIPLE CLOCK DOMAINS; PHYSICAL DESIGN; PLACEMENT; RECENT PROGRESS; SOFTWARE IMPLEMENTATION;

ALGORITHMS; ELECTRIC CLOCKS; LOW POWER ELECTRONICS; OPTIMIZATION;

FORESTRY;

ALGORITHMS; CLOCKS; ELECTRONICS; FORESTRY; OPTIMIZATION;

EID: 84863011686     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2173490     Document Type: Conference Paper

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