Post-placement power optimization with multi-bit flip-flops

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2010, Pages 218-223

  Chang, Yao Tsung ^a   Hsu, Chih Cheng ^a   Lin, Mark Po Hung ^a   Tsai, Yu Wen ^b   Chen, Sheng Fong ^b  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^b FARADAY TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTER AIDED DESIGN; ECONOMIC AND SOCIAL EFFECTS;

CLOCK NETWORK; DESIGN FLOWS; DESIGN OBJECTIVES; DESIGN STAGE; INDUSTRY BENCHMARKS; POWER OPTIMIZATION; POWER SAVINGS; TIMING SLACK;

FLIP FLOP CIRCUITS;

EID: 78650883034     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2010.5654155     Document Type: Conference Paper

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