History-based VLSI legalization using network flow

Proceedings - Design Automation Conference

Volumn , Issue , 2010, Pages 286-291

  Cho, Minsik ^a   Ren, Haoxing ^a   Xiang, Hua ^a   Puri, Ruchir ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Legalization; Network flow; Placement; VLSI

Indexed keywords

COMPLEX DESIGNS; FAILURE RATE; LEGAL SOLUTIONS; LEGALIZATION; NETWORK FLOW FORMULATION; NETWORK FLOWS; PLACEMENT; QUALITY OF RESULTS; SUBSET-SUM PROBLEM; VLSI; VLSI PLACEMENT;

ALGORITHMS; AUTHENTICATION; COMPUTER AIDED DESIGN;

CONTRACTS;

EID: 77956221573     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1837274.1837347     Document Type: Conference Paper

References (16)

1. A. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, and P. H. Madden. Fractional cut: Improved recursive bisection placement. In Proc. Int. Conf. on Computer Aided Design, 2003.
2. U. Brenner, A. Pauli, and J. Vygen. Almost optimum placement legalization by minimum cost flow and dynamic programming. In Proc. Int. Symp. on Physical Design, 2004.
3. U. Brenner and J. Vygen. Faster optimal single-row placement with fixed ordering. In Proc. Design, Automation and Test in Eurpoe, 2000.
4. U. Brenner and J. Vygen. Legalizing a placement with minimum total movement. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 23(12):1597-1613,Dec 2004.
5. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 27(7):1228-1240, Jul 2008.
6. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. Introduction to Algorithms, Second Edition. MIT Press and McGraw-Hill, 2001.
7. M. R. Garey, R. E. Tarjan, and G. T. Wilfong. One-processor scheduling with symmetric earliness and tardiness penalties. Math. Oper. Res., 13(2), 1988.
8. A. V. Goldberg. An Effcient Implementation of a Scaling Minimum-Cost Flow Algorithmn. Journal of Algorithms, 22:1-29, 1997.
9. D. Hill. Method and system for high speed detailed placement of cells within an integrated circuit design". In U.S. Patent 6370673, Apr 2002.
10. S. W. Hur and J. Lillis. Mongrel: hybrid techniques for standard cell placement. In Proc. Int. Conf. on Computer Aided Design, 2000.
11. A. Kahng, P. Tucker, and A. Zelikovsky. Optimization of linear placements for wirelength minimization with free sites. In Proc. Asia and South Pacific Design Automation Conf., 1999.
12. T. Luo, H. Ren, C. J. Alpert, and D. Z. Pan. Computational geometry based placement migration. In Proc. Int. Conf. on Computer Aided Design, 2005.
13. D. Pisinger. Linear time algorithms for knapsack problems with bounded weights. Journal of Algorithms, 33:1-14, 1999.
14. H. Ren, D. Z. Pan, C. J. Alpert, and P. Villarrubia. Diffusion-based placement migration. In Proc. Design Automation Conf., 2005.
15. T. Taghavi, X. Yang, B.-K. Choi, M. Wang, and M. Sarrafzadeh. Dragon2006: blockage-aware congestion-controlling mixed-size placer. In Proc. Int. Symp. on Physical Design.
16. N. Viswanathan, M. Pan, and C. Chu. Fastplace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control. In Proc. Asia and South Pacific Design Automation Conf., 2007.