Interconnect-power dissipation in a microprocessor

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2004, Pages 7-13

  Magen, Nir ^a   Kolodny, Avinoam ^b   Weiser, Uri ^a   Shamir, Nachum ^a  

^a INTEL CORPORATION   (Israel)

^b TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Interconnect power; Low power design; Routing; Wire spacing

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT LAYOUT; ROUTERS; STRESS ANALYSIS; SWITCHING;

INTERCONNECT POWER; LOW-POWER DESIGN; ROUTING; WIRE SPACING;

MICROPROCESSOR CHIPS;

EID: 16244422171     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/966748.966750     Document Type: Conference Paper

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