Design-hierarchy aware mixed-size placement for routability optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2010, Pages 663-668

  Chuang, Yi Lin ^a   Nam, Gi Joon ^b   Alpert, Charles J ^b   Chang, Yao Wen ^a   Roy, Jarrod ^b   Viswanathan, Natarajan ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FENCES; PLACERS;

ANALYTICAL PLACEMENT; BOUNDING BOX; CIRCUIT PLACEMENT; DESIGN HIERARCHY; MIXED-SIZE PLACEMENT; STANDARD CELL; STATE OF THE ART; WIRELENGTH MINIMIZATION;

MACROS;

EID: 78650900700     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2010.5654234     Document Type: Conference Paper

References (18)

1. C. Alpert, A. Kahng, G.-J. Nam, S. Reda, and P. Villarrubia. A semipersistent clustering technique for VLSI circuit placement. In Proc. of ISPD, 2005.
2. T. Chan, J. Cong, J. Shinned, K. Sze, and M. XIe. mPL6: Enhanced multilevel mixed-size placement. In Proc. of ISPD, 2006.
3. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. In IEEE TCAD, 2008.
4. T.-C. Chen, M. Cho, D. Z. Pan, and Y.-W. Chang. Metal-density driven placement for CMP variation and routability. In Proc. of ISPD, 2008.
5. Y. Cheon and D. F. Wong. Design hierarchy guided multilevel circuit partitioning. In Proc. of ISPD, 2002.
6. C. Chu and Y-C. Wong. Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. In Proc. of ISPD, 2005.
7. J. Fischer and V. Heun. Theoretical and practical improvements on the RMQ-problem, with applications to LCA and LCE. In Proc. of CPM, 2006.
8. J. Hu, J. A. Roy, and I. L. Markov. Completing high-quality global routes. In Proc. of ISPD, 2010.
9. ISPD 2005 Placement Contest. http://www.sigda.org/ispd2005/contest.htm.
10. ISPD 2007 Routing Contest, http://www.sigda.org/ispd2007/contest.html.
11. Z.-W. Jiang, B.-Y. Su, and Y-W. Chang. Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. In Proc. of DAC, 2008.
12. A. B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. In IEEE TCAD, 2005.
13. W. C. Naylor, R. Donelly, and L. Sha. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. U.S. Patent 6 301 693, 2001.
14. J. A. Roy, S. N. Adya, D. A. Papa, and I. L. Markov. Min-cut floorplacement. In Proc. of TCAD, 2006.
15. J. A. Roy and I. L. Markov. High-performance routing at the nanometer scale. In Proc. of ICCAD, 2007.
16. J. A. Roy, J. F. Lu, and I. L. Markov. Seeing the forest and the trees: Steiner wirelength optimization in placement. In IEEE TCAD, 2007.
17. J. Westra, C. Bartels, and P. Geoeneveld. Probabilistic congestion prediction. In Proc. of ISPD, 2004.
18. J. Z. Yan, N. Viswanathan, and C. Chu. Handling complexities in modern large-scale mixed-size placement. In Proc. of DAC, 2009.