Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization

Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Volumn , Issue , 2010, Pages 369-374

  Ho, Tsung Yi ^a   Liu, Sheng Hung ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP PERFORMANCE; CLUSTERING APPROACH; CONSTANT TIME; CRITICAL STEPS; MAXIMUM DISPLACEMENT; ROUTABILITY; RUNNING TIME; SELECTION TECHNIQUES; SOC DESIGNS; STANDARD-CELL PLACEMENT; TIMING-DRIVEN; WIRE LENGTH;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTHENTICATION; CONTRACTS; ELECTRIC BATTERIES; OPTIMIZATION;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 78650937558     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2010.5642689     Document Type: Conference Paper

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