메뉴 건너뛰기




Volumn 27, Issue 5, 2010, Pages 14-24

Speeding up physical synthesis with transactional timing analysis

Author keywords

[No Author keywords available]

Indexed keywords

INCREMENTAL UPDATES; LARGE DESIGNS; PHYSICAL SYNTHESIS; TIMING ANALYSIS; TIMING OPTIMIZATION;

EID: 78649262903     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2010.76     Document Type: Article
Times cited : (5)

References (18)
  • 1
    • 1342323840 scopus 로고    scopus 로고
    • An integrated environment for technology closure of deep-submicron ic designs
    • L. Trevillyan et al., "An Integrated Environment for Technology Closure of Deep-Submicron IC Designs," IEEE Design & Test, vol. 21, no. 1, 2004, pp. 14-22.
    • (2004) IEEE Design & Test , vol.21 , Issue.1 , pp. 14-22
    • Trevillyan, L.1
  • 4
    • 43349101482 scopus 로고    scopus 로고
    • Rumble: An incremental, timing-driven, physical-synthesis optimization algorithm
    • ACM Press
    • D.A. Papa et al., "Rumble: An Incremental, Timing-Driven, Physical-Synthesis Optimization Algorithm," Proc. Int'l Symp. Physical Design (ISPD 08), ACM Press, 2008, pp. 2-9.
    • (2008) Proc. Int'l Symp. Physical Design (ISPD 08) , pp. 2-9
    • Papa, D.A.1
  • 8
    • 78649233148 scopus 로고    scopus 로고
    • US patent 5 to IBM Corp., Patent and Trademark Office
    • R.P. Abato et al., Incremental Timing Analysis, US patent 5,508,937, to IBM Corp., Patent and Trademark Office, 1996.
    • (1996) Incremental Timing Analysis , vol.508 , pp. 937
    • Abato, R.P.1
  • 10
    • 0029708044 scopus 로고    scopus 로고
    • Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits
    • IEEE Press
    • S.S. Sapatnekar, "Efficient Calculation of All-Pairs Input-to-Output Delays in Synchronous Sequential Circuits," Proc. Int'l Symp. Circuits and Systems (ISCAS 96), IEEE Press, 1996, pp. 724-727.
    • (1996) Proc. Int'l Symp. Circuits and Systems (ISCAS 96) , pp. 724-727
    • Sapatnekar, S.S.1
  • 11
  • 12
    • 49749103181 scopus 로고    scopus 로고
    • FA-STAC: A framework for fast and accurate static timing analysis with coupling
    • IEEE Press
    • D. Das et al., "FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling," Proc. Int'l Conf. Computer Design (ICCD 06), IEEE Press, 2006, pp. 43-49.
    • (2006) Proc. Int'l Conf. Computer Design (ICCD 06) , pp. 43-49
    • Das, D.1
  • 14
    • 78649307103 scopus 로고    scopus 로고
    • Static timing analysis increases ASIC performance
    • June
    • D. Bronnenberg, "Static Timing Analysis Increases ASIC Performance," Integrated System Design, June 1999.
    • (1999) Integrated System Design
    • Bronnenberg, D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.