Timing optimization by restructuring long combinatorial paths

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 536-543

  Werber, Jürgen ^a   Rautenbach, Dieter ^b   Szegedy, Christian ^c  

^a UNIVERSITY OF BONN   (Germany)

^b ILMENAU UNIVERSITY OF TECHNOLOGY   (Germany)

^c CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; INDUSTRIAL ECONOMICS; NETWORKS (CIRCUITS); OPTIMIZATION; TIME MEASUREMENT;

COMPUTER-AIDED DESIGN; CRITICAL PATHS; INDUSTRIAL CHIPS; INPUT SIGNALS; INTERNATIONAL CONFERENCES; LOGIC OPTIMIZATION; PICOSECONDS; TIMING OPTIMIZATION; VLSI PHYSICAL DESIGN;

BOOLEAN FUNCTIONS;

EID: 50249173469     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397320     Document Type: Conference Paper

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