Making fast buffer insertion even faster via approximation techniques

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 13-18

  Li, Zhuo ^a   Sze, C N ^a   Alpert, Charles J ^b   Hu, Jiang ^a   Shi, Weiping ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; COMPUTER AIDED DESIGN;

APPROXIMATION TECHNIQUES; BUFFER INSERTION; CRITICAL PATHS; DELAY PENALTY; FAST IMPLEMENTATION; LOOKUPS; PHYSICAL SYNTHESIS; SPEED UP;

APPROXIMATION ALGORITHMS;

EID: 79952149496     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120733     Document Type: Conference Paper

References (15)

1. P. Saxena, N- Menezes, P. Cocchini, and D. A. Kirkpatrick, "Repeater scaling and its impact on cad," IEEE Trans. CAD, vol. 23, no. 4, pp. 451-463,2004.
2. P. J. Osier, "Placement driven synthesis case studies on two sets of two chips: Hierarchical and flat," in ISPD, 2004, pp. 190-197.
3. L. P. P. P. van Cinneken, "Buffer placement in distributed RC-lree network for minimal elmore delay," in ISCAS, 1990. pp. 865-868.
4. W. Shi and Z. Li, "A Fast Algorithm for Fast Buffer Insertion," IEEE Trans. CAD, to appear.
5. W. Shi and Z. Li, "An O(nlogn) time algorithm for optimal buffer inser-tion," in DAC, 2003, pp. 580-585.
6. J. Lillis, C. K. Cheng, and T.-T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE Trans. Solid-Stale Circuits, vol. 31, no. 3, pp. 437-447, 1996.
7. C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion with accurate gate and interconnect delay computation," in DAC, 1999, pp. 479-484.
8. C.-P. Chen and N. Menezes, "Noise-aware repeater insertion and wire sizing for on-chip interconnect using hierarchical moment matching," in DAC, 1999, pp. 502-506.
9. T. Okamoto and J. Cong, "Buffered steiner tree construction with wire sizing for interconnect layout optimization," in ICCAD, 1996, pp. 44-49.
10. M. Hrkic and J. Lillis, "S-tree: a technique for buffered routing tree synthesis," in DAC, 2002, pp. 578-583.
11. M. Hrkic and J. Lillis, "Buffer tree synthesis with consideration of temporal locality," sink polarity requirements, solution cost and blockages," in ISPD, 2002, pp. 98-103.
12. J. Hu, C. J. Alpert, S. T. Quay and G. Gandham, "Buffer insertion with adaptive blokage avoidance," IEEE Trans. CAD, vol. 22, no. 4, pp. 492-498,2003.
13. C. J. Alpert. A, Devgan, and S. T, Quay, "Buffer insertion for noise and delay optimization," in DAC, 1998, pp. 362-367
14. W. Shi, Z. Li, and C. J. Alpert, "Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost" in ASPDAC, 2004, pp. 609-614.
15. C. J. Alpert, R. G. Gandham, J. L. Neves, and S. T. Quay, "Buffer library selection," in ICCD, 2000, pp, 221-226.