Lens aberration aware placement for timing yield

ACM Transactions on Design Automation of Electronic Systems

Volumn 14, Issue 1, 2009, Pages

  Kahng, Andrew B ^a   Park, Chul Hong ^a   Sharma, Puneet ^b   Wang, Qinke ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c MAGMA DESIGN AUTOMATION   (United States)

Author keywords

Design for manufacturing; Layout; Lithography; Timing yield

Indexed keywords

90 NM TECHNOLOGIES; ANALYTICAL PLACEMENTS; CELL DELAY VARIATIONS; CYCLE TIME; CYCLE TIME REDUCTIONS; DESIGN FOR MANUFACTURING; DESIGN PHASE; LAYOUT; LENS ABERRATIONS; LITHOGRAPHY; ON CHIPS; PROCESS MARGINS; PROCESS VARIATIONS; RETICLE ENHANCEMENT TECHNIQUES; TEST-CASES; TIMING ANALYSIS; TIMING YIELD; TIMING-DRIVEN; WIRE LENGTHS;

CAMERA LENSES; LENSES; OPTICAL INSTRUMENTS; TIME MEASUREMENT;

ABERRATIONS;

EID: 60349130059     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1455229.1455245     Document Type: Article

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