Physical synthesis with clock-network optimization for large systems on chips

IEEE Micro

Volumn 31, Issue 4, 2011, Pages 51-62

  Papa, David ^a   Viswanathan, Natarajan ^b   Sze, Cliff ^b   Li, Zhuo ^b   Nam, Gi Joon ^b   Alpert, Charles ^b   Markov, Igor L ^c  

^a Broadway Technology   (United States)

^b IBM   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

physical synthesis; systems on chips

Indexed keywords

CPU DESIGN; CURRENT TECHNOLOGY; ELECTRONIC DESIGN AUTOMATION; LARGE SYSTEM; PHYSICAL SYNTHESIS; SYSTEMS ON CHIPS; WIRE LENGTH;

FLIP FLOP CIRCUITS;

EID: 79961096575     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2011.41     Document Type: Article

References (9)

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