메뉴 건너뛰기




Volumn , Issue , 2012, Pages 161-164

The ISPD-2012 discrete cell sizing Contest and benchmark suite

Author keywords

Benchmarks; Circuit optimization; Gate sizing; Physical Design

Indexed keywords

BENCHMARK SUITES; BENCHMARKS; CIRCUIT OPTIMIZATION; DISCRETE CELLS; EVALUATION METRICS; GATE SIZING; PHYSICAL DESIGN; STANDARD CELL; TIMING CONSTRAINTS; TIMING MODELS; VOLTAGE ASSIGNMENT;

EID: 84860237262     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2160916.2160950     Document Type: Conference Paper
Times cited : (85)

References (10)
  • 1
    • 84962312902 scopus 로고
    • Gate sizing in MOS digital circuits with linear programming
    • M. R. C. M. Berkelaar and J. A. G. Jess. Gate sizing in MOS digital circuits with linear programming. In Proc. of DATE, pages 217-221, 1990.
    • (1990) Proc. of DATE , pp. 217-221
    • Berkelaar, M.R.C.M.1    Jess, J.A.G.2
  • 2
    • 0032685389 scopus 로고    scopus 로고
    • Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
    • July
    • C. P. Chen, C. C.-N. Chu, and D. F. Wong. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. on Computer-Aided Design, 18(7):1014-1025, July 1999.
    • (1999) IEEE Trans. on Computer-Aided Design , vol.18 , Issue.7 , pp. 1014-1025
    • Chen, C.P.1    Chu, C.C.-N.2    Wong, D.F.3
  • 4
    • 84861419836 scopus 로고    scopus 로고
    • Fast and effective gate sizing with multiple-Vt assignment using generalized Lagrangian relaxation
    • H. Chou, Y.-H. Wang, and C. C.-P. Chen. Fast and effective gate sizing with multiple-Vt assignment using generalized Lagrangian relaxation. In Proc. of ASPDAC, pages 381-386, 2005.
    • (2005) Proc. of ASPDAC , pp. 381-386
    • Chou, H.1    Wang, Y.-H.2    Chen, C.C.-P.3
  • 5
    • 84862921936 scopus 로고    scopus 로고
    • Gate sizing and device technology selection algorithms for high-performance industrial designs
    • Nov.
    • M. M. Ozdal, S. Burns, and J. Hu. Gate sizing and device technology selection algorithms for high-performance industrial designs. In Proc. of ICCAD, Nov. 2011.
    • (2011) Proc. of ICCAD
    • Ozdal, M.M.1    Burns, S.2    Hu, J.3
  • 6
    • 79957562268 scopus 로고    scopus 로고
    • Power reduction via near-optimal library-based cell-size selection
    • M. Rahman, H. Tennakoon, and C. Sechen. Power reduction via near-optimal library-based cell-size selection. In Proc. of DATE, 2011.
    • (2011) Proc. of DATE
    • Rahman, M.1    Tennakoon, H.2    Sechen, C.3
  • 9
    • 0036911571 scopus 로고    scopus 로고
    • Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
    • H. Tennakoon and C. Sechen. Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. In Proc. of ICCAD, pages 395-402, 2002.
    • (2002) Proc. of ICCAD , pp. 395-402
    • Tennakoon, H.1    Sechen, C.2
  • 10
    • 67650917100 scopus 로고    scopus 로고
    • Gate sizing by Lagrangian relaxation revisited
    • July
    • J. Wang, D. Das, and H. Zhou. Gate sizing by Lagrangian relaxation revisited. IEEE Trans. on Computer-Aided Design, 28(7):1071-1084, July 2009.
    • (2009) IEEE Trans. on Computer-Aided Design , vol.28 , Issue.7 , pp. 1071-1084
    • Wang, J.1    Das, D.2    Zhou, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.