Activity and register placement aware gated clock network design

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2008, Pages 182-189

  Weixiang, Shen ^a   Yici, Cai ^a   Xianlong, Hong ^a   Jiang, Hu ^b  

^a TSINGHUA UNIVERSITY   (China)

^b Department of Electrical and Computer Engineering   (United States)

Author keywords

Gated clock tree; Low power; Placement

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK TOPOLOGY; ENERGY DISSIPATION; LOGIC DESIGN;

CLOCK GATING; FREQUENT CONTROL SIGNAL SWITCHING; GATED CLOCK TREE;

ELECTRIC POWER TRANSMISSION NETWORKS;

EID: 43349085862     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1353629.1353668     Document Type: Conference Paper

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