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Volumn 2006, Issue , 2006, Pages 582-587

Power driven placement with layout aware supply voltage assignment for voltage island generation in dual-Vdd designs

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CONSTRAINT THEORY; ELECTRIC POTENTIAL; WIRE PRODUCTS;

EID: 33748593901     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118437     Document Type: Conference Paper
Times cited : (38)

References (21)
  • 1
    • 0029193696 scopus 로고    scopus 로고
    • Clustered voltage scaling technique for low-power design
    • K. Usami and M. Horowitz, "Clustered voltage scaling technique for low-power design, " in Proc. ISLPED'95, pp. 3-8.
    • Proc. ISLPED'95 , pp. 3-8
    • Usami, K.1    Horowitz, M.2
  • 2
    • 0035472548 scopus 로고    scopus 로고
    • On gate level power optimization using dual-supply voltages
    • Oct.
    • C. Chen, A. Srivastava and M. Sarrafzadeh, "On gate level power optimization using dual-supply voltages," IEEE Trans. on VLSI Syst., vol. 9, pp. 616-629, Oct. 2001.
    • (2001) IEEE Trans. on VLSI Syst. , vol.9 , pp. 616-629
    • Chen, C.1    Srivastava, A.2    Sarrafzadeh, M.3
  • 3
    • 0036911921 scopus 로고    scopus 로고
    • Managing power and performance for system-on-chip designs using voltage islands
    • Nov.
    • D.E. Lackey, P.S. Zuchowski, T.R. Bednar, D.W. Stout, S.W. Gould, and J.M. Cohn, "Managing power and performance for system-on-chip designs using voltage islands," in ICCAD'02, pp. 195-202, Nov. 2002.
    • (2002) ICCAD'02 , pp. 195-202
    • Lackey, D.E.1    Zuchowski, P.S.2    Bednar, T.R.3    Stout, D.W.4    Gould, S.W.5    Cohn, J.M.6
  • 4
    • 33748599126 scopus 로고    scopus 로고
    • A new algorithm for improved VDD assignment in low power dual VDD systems
    • S.H. Kulkarni, A.N. Srivastava, and D. Sylvester, "A new algorithm for improved VDD assignment in low power dual VDD systems," in Proc. ISLPED'04, pp.200-205.
    • Proc. ISLPED'04 , pp. 200-205
    • Kulkarni, S.H.1    Srivastava, A.N.2    Sylvester, D.3
  • 5
    • 4444327756 scopus 로고    scopus 로고
    • Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
    • A. Srivastava, D. Sylvester and D. Blaauw, "Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment," in Proc. DAC'04, pp.783-787.
    • Proc. DAC'04 , pp. 783-787
    • Srivastava, A.1    Sylvester, D.2    Blaauw, D.3
  • 8
    • 84932170042 scopus 로고    scopus 로고
    • Architecting voltage islands in core-based system-on-a-chip designs
    • J. Hu, Y. Shin, N. Dhanwada and Radu Marculescu, "Architecting voltage islands in core-based system-on-a-chip designs," in Proc. ISLPED'04, pp.180-185.
    • Proc. ISLPED'04 , pp. 180-185
    • Hu, J.1    Shin, Y.2    Dhanwada, N.3    Marculescu, R.4
  • 9
    • 1642317047 scopus 로고    scopus 로고
    • Level conversion for dual-supply systems
    • Feb.
    • F. Ishihara, F. Sheikh and B. Nikolic, "Level conversion for dual-supply systems," IEEE Trans. VLSI Syst., vol. 12, pp.185-195, Feb. 2004.
    • (2004) IEEE Trans. VLSI Syst. , vol.12 , pp. 185-195
    • Ishihara, F.1    Sheikh, F.2    Nikolic, B.3
  • 10
    • 0032690059 scopus 로고    scopus 로고
    • Layout techniques supporting the use of dual supply voltages for cell-based designs
    • C. Yeh, Y. Kang, S. Shieh and J. Wang, "Layout techniques supporting the use of dual supply voltages for cell-based designs," in Proc. DAC'99, pp.62-67.
    • Proc. DAC'99 , pp. 62-67
    • Yeh, C.1    Kang, Y.2    Shieh, S.3    Wang, J.4
  • 14
    • 33748592433 scopus 로고    scopus 로고
    • private communication
    • P.H. Madden, private communication.
    • Madden, P.H.1
  • 15
    • 0036375925 scopus 로고    scopus 로고
    • Min-max placement for large-scale timing optimization
    • A.B. Kahng, S. Mantik and I.L. Markov, "Min-max placement for large-scale timing optimization," in Proc. ISPD'02, pp. 143-148.
    • Proc. ISPD'02 , pp. 143-148
    • Kahng, A.B.1    Mantik, S.2    Markov, I.L.3
  • 16
    • 0033697586 scopus 로고    scopus 로고
    • Can recursive bisection alone produce routable placements?
    • A.E. Caldwell, A.B. Kahng, and I.L. Markov, "Can recursive bisection alone produce routable placements?," in Proc. DAC'00, pp.477-482.
    • Proc. DAC'00 , pp. 477-482
    • Caldwell, A.E.1    Kahng, A.B.2    Markov, I.L.3
  • 17
    • 4444341110 scopus 로고    scopus 로고
    • Placement feedback: A concept and method for better min-cut placements
    • A.B. Kahng and S. Reda, "Placement feedback: a concept and method for better min-cut placements," in Proc. DAC'04, pp.357-362.
    • Proc. DAC'04 , pp. 357-362
    • Kahng, A.B.1    Reda, S.2
  • 18
    • 0036907067 scopus 로고    scopus 로고
    • A novel net weighting algorithm for timing-driven placement
    • T. Kong, "A novel net weighting algorithm for timing-driven placement," in Proc. ICCAD'02, pp.172-176.
    • Proc. ICCAD'02 , pp. 172-176
    • Kong, T.1
  • 19
    • 18744393753 scopus 로고    scopus 로고
    • Implementation and extensibility of an analytic placer
    • May
    • A.B. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer," IEEE Trans. Computer-Aided Design, vol. 24, pp.734-747, May 2005.
    • (2005) IEEE Trans. Computer-aided Design , vol.24 , pp. 734-747
    • Kahng, A.B.1    Wang, Q.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.