-
1
-
-
0029193696
-
Clustered voltage scaling technique for low-power design
-
K. Usami and M. Horowitz, "Clustered voltage scaling technique for low-power design, " in Proc. ISLPED'95, pp. 3-8.
-
Proc. ISLPED'95
, pp. 3-8
-
-
Usami, K.1
Horowitz, M.2
-
2
-
-
0035472548
-
On gate level power optimization using dual-supply voltages
-
Oct.
-
C. Chen, A. Srivastava and M. Sarrafzadeh, "On gate level power optimization using dual-supply voltages," IEEE Trans. on VLSI Syst., vol. 9, pp. 616-629, Oct. 2001.
-
(2001)
IEEE Trans. on VLSI Syst.
, vol.9
, pp. 616-629
-
-
Chen, C.1
Srivastava, A.2
Sarrafzadeh, M.3
-
3
-
-
0036911921
-
Managing power and performance for system-on-chip designs using voltage islands
-
Nov.
-
D.E. Lackey, P.S. Zuchowski, T.R. Bednar, D.W. Stout, S.W. Gould, and J.M. Cohn, "Managing power and performance for system-on-chip designs using voltage islands," in ICCAD'02, pp. 195-202, Nov. 2002.
-
(2002)
ICCAD'02
, pp. 195-202
-
-
Lackey, D.E.1
Zuchowski, P.S.2
Bednar, T.R.3
Stout, D.W.4
Gould, S.W.5
Cohn, J.M.6
-
4
-
-
33748599126
-
A new algorithm for improved VDD assignment in low power dual VDD systems
-
S.H. Kulkarni, A.N. Srivastava, and D. Sylvester, "A new algorithm for improved VDD assignment in low power dual VDD systems," in Proc. ISLPED'04, pp.200-205.
-
Proc. ISLPED'04
, pp. 200-205
-
-
Kulkarni, S.H.1
Srivastava, A.N.2
Sylvester, D.3
-
5
-
-
4444327756
-
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
-
A. Srivastava, D. Sylvester and D. Blaauw, "Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment," in Proc. DAC'04, pp.783-787.
-
Proc. DAC'04
, pp. 783-787
-
-
Srivastava, A.1
Sylvester, D.2
Blaauw, D.3
-
6
-
-
11944260934
-
A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS
-
Jan.
-
S.K. Mathew, M.A. Anders, B. Bloechel, T. Nguyen, R.K. Krishnamurthy and S. Borkar, "A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 40, pp.44-51, Jan. 2005.
-
(2005)
IEEE J. Solid-state Circuits
, vol.40
, pp. 44-51
-
-
Mathew, S.K.1
Anders, M.A.2
Bloechel, B.3
Nguyen, T.4
Krishnamurthy, R.K.5
Borkar, S.6
-
7
-
-
0042635592
-
Pushing ASIC performance in a power envelope
-
R. Puri, L. Stok, J. Cohn, D. Kung, D. Pan, D. Sylvester, A. Srivastava and S. Kulkarni "Pushing ASIC performance in a power envelope," in Proc. DAC'03, pp.788-793.
-
Proc. DAC'03
, pp. 788-793
-
-
Puri, R.1
Stok, L.2
Cohn, J.3
Kung, D.4
Pan, D.5
Sylvester, D.6
Srivastava, A.7
Kulkarni, S.8
-
8
-
-
84932170042
-
Architecting voltage islands in core-based system-on-a-chip designs
-
J. Hu, Y. Shin, N. Dhanwada and Radu Marculescu, "Architecting voltage islands in core-based system-on-a-chip designs," in Proc. ISLPED'04, pp.180-185.
-
Proc. ISLPED'04
, pp. 180-185
-
-
Hu, J.1
Shin, Y.2
Dhanwada, N.3
Marculescu, R.4
-
9
-
-
1642317047
-
Level conversion for dual-supply systems
-
Feb.
-
F. Ishihara, F. Sheikh and B. Nikolic, "Level conversion for dual-supply systems," IEEE Trans. VLSI Syst., vol. 12, pp.185-195, Feb. 2004.
-
(2004)
IEEE Trans. VLSI Syst.
, vol.12
, pp. 185-195
-
-
Ishihara, F.1
Sheikh, F.2
Nikolic, B.3
-
10
-
-
0032690059
-
Layout techniques supporting the use of dual supply voltages for cell-based designs
-
C. Yeh, Y. Kang, S. Shieh and J. Wang, "Layout techniques supporting the use of dual supply voltages for cell-based designs," in Proc. DAC'99, pp.62-67.
-
Proc. DAC'99
, pp. 62-67
-
-
Yeh, C.1
Kang, Y.2
Shieh, S.3
Wang, J.4
-
14
-
-
33748592433
-
-
private communication
-
P.H. Madden, private communication.
-
-
-
Madden, P.H.1
-
15
-
-
0036375925
-
Min-max placement for large-scale timing optimization
-
A.B. Kahng, S. Mantik and I.L. Markov, "Min-max placement for large-scale timing optimization," in Proc. ISPD'02, pp. 143-148.
-
Proc. ISPD'02
, pp. 143-148
-
-
Kahng, A.B.1
Mantik, S.2
Markov, I.L.3
-
16
-
-
0033697586
-
Can recursive bisection alone produce routable placements?
-
A.E. Caldwell, A.B. Kahng, and I.L. Markov, "Can recursive bisection alone produce routable placements?," in Proc. DAC'00, pp.477-482.
-
Proc. DAC'00
, pp. 477-482
-
-
Caldwell, A.E.1
Kahng, A.B.2
Markov, I.L.3
-
17
-
-
4444341110
-
Placement feedback: A concept and method for better min-cut placements
-
A.B. Kahng and S. Reda, "Placement feedback: a concept and method for better min-cut placements," in Proc. DAC'04, pp.357-362.
-
Proc. DAC'04
, pp. 357-362
-
-
Kahng, A.B.1
Reda, S.2
-
18
-
-
0036907067
-
A novel net weighting algorithm for timing-driven placement
-
T. Kong, "A novel net weighting algorithm for timing-driven placement," in Proc. ICCAD'02, pp.172-176.
-
Proc. ICCAD'02
, pp. 172-176
-
-
Kong, T.1
-
19
-
-
18744393753
-
Implementation and extensibility of an analytic placer
-
May
-
A.B. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer," IEEE Trans. Computer-Aided Design, vol. 24, pp.734-747, May 2005.
-
(2005)
IEEE Trans. Computer-aided Design
, vol.24
, pp. 734-747
-
-
Kahng, A.B.1
Wang, Q.2
-
20
-
-
27944481842
-
Power aware placement
-
Y. Cheon, P.H. Ho, A.B. Kahng, S. Reda and Q. Wang, "Power aware placement," in Proc. DAC'05, pp.795-800.
-
Proc. DAC'05
, pp. 795-800
-
-
Cheon, Y.1
Ho, P.H.2
Kahng, A.B.3
Reda, S.4
Wang, Q.5
-
21
-
-
33748606515
-
Min-cut floorplacement
-
to appear
-
J.A. Roy, S.N. Adya, D.A. Papa and I.L. Markov, "Min-cut floorplacement,", IEEE Trans. on Computer-Aided Design, to appear.
-
IEEE Trans. on Computer-aided Design
-
-
Roy, J.A.1
Adya, S.N.2
Papa, D.A.3
Markov, I.L.4
|