Register placement for high-performance circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 1470-1475

  Chiang, Mei Fang ^a   Okamoto, Takumi ^b   Yoshimura, Takeshi ^a  

^a WASEDA UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK DISTRIBUTION; CLOCK TREE SYNTHESIS; CONFLICT GRAPH; GLOBAL CLOCKS; GRAPH SIZES; HIGH-PERFORMANCE CIRCUITS; KEY COMPONENT; MANHATTANS; MAXIMUM INDEPENDENT SETS; PLACEMENT PROBLEMS; SUBMICRON; TECHNOLOGY NODES; TWO STAGE;

ELECTRIC CLOCKS; HEURISTIC METHODS; INTEGRATED CIRCUIT MANUFACTURE; SET THEORY; WIRELESS TELECOMMUNICATION SYSTEMS;

DESIGN;

EID: 70350062055     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

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