Sensitivity based placer for standard cells

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2000, Pages 193-196

  Halpin, Bill ^a   Chen, C Y Roger ^a   Sehgal, Naresh ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; SEMICONDUCTOR DEVICE MODELS; SENSITIVITY ANALYSIS;

TIMING DRIVEN ALGORITHMS;

LOGIC GATES;

EID: 0033701024     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)