Floorplan management: Incremental placement for gate sizing and buffer insertion

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 349-354

  Li, Chen ^a   Koh, Cheng Kok ^a   Madden, Patrick H ^b  

^a PURDUE UNIVERSITY   (United States)

^b BINGHAMTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER INSERTION; DESIGN CLOSURE; FLOORPLAN SIZING; FLOORPLANS; GATE SIZING; INCREMENTAL CHANGES; INCREMENTAL PLACEMENT; LARGE-SCALE CIRCUITS; NETLIST; PHYSICAL DESIGN; PHYSICAL SYNTHESIS; PLACEMENT TOOLS; WIRE LENGTH;

BUFFER CIRCUITS; COMPUTER AIDED DESIGN;

GATES (TRANSISTOR);

EID: 29144440605     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. S. Adya, I. Markov, and P. Villmbia. On whitespace and stability in mixed-size placement and physical synthesis. In Proc. Int. Conf. on Compurer Aided Design, pages 31 1-318, 2003.
2. A. E. Caldwell, A. B. Kahng, and I. L. Markov. Optimal panitioners and end-case placers for standard-cell layout. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 19( 11):1304-1313, 2000.
3. T. Chan, J. Cong, T. Kong, 1. Shinned, and K. Sze. An enhanced multilevel algorithm for circuit placement. In Proc. Int. Conf. on Computer Aided Design, pages 299-306. 2003.
4. Y-H. Chan, P. Kudva, L. Lacey, G, Northrop, and T. Rosser. Physical synthesis methodology for high performance microprocessors. In Proc. Design Automation Conf, pages 696-701, 2003.
5. C.-C. Chang, J. Cong, and M. Xie. Optimality and scalability study of existing placement algorithms. In Proc. Asia South Pacific Design Automation Conf., pages 621-427, 2003.
6. W. Chen, C. Hsieh, and M. Fedram. Simultaneously gate sizing and placement. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 19(2):20-214, 2000.
7. J. Cong. Challenges and opportunities for design innovations in nanometer technologies. In Frontiers in Semiconductor Research: A Collection of SRC Working Papers. Semiconductor Research Corp., 1997.
8. J. Cong and M. Sarrafzadeh. Incremental physical design. In Proc. Int. Symp. on Physical Design, pages 3442. 2000.
9. A. Khatkhate, C. Li, A. Agnihotri, M. Yddiz, S. Ono, C.-K. Koh, and P. Madden. Recursive bisection based mixed block placement. In Proc. Int. Symp. on Physical Design, pages 84-89, 2004.
10. L. P. P. P. van Ginneken. Buffer placement in distnbuted rc-tree networks for minimal Elmore delay. In Proc. IEEE Int. Symp. on Circuits and System, pages 865-868, 1990.
11. C. Li, M. Xie, C.-K. Koh, J. Cong, and P. H Madden. Roumbility-driven placement and white space allocation. In Proc. Int. Conf. on Computer Aided Design, 2004.
12. P. Saxena and B. Halpin. Modeling repeaters explicitly within analytical placement. In Proc. Design Automation Conf. pages 699-704, 2004.
13. P. Saxena, N. Meneres, P. Cocchini, and D. A. Kirkpartrick. Repeater scaling and its impact on CAD. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 23(4);451-463, 2004.
14. G. Stenz, B. M. Riess, B. Rohfeisch, and E M. Johannes. Timing driven placement in interaction with netlist transformations. In Proc. Inr. Symp. on Physicol Design. pages 36-41, 1997.
15. M. Vujkovic, D. Wadkins, B. Swartz, and C. Sechen. Efficient timing closure without timing driven placement and routing. In Proc. Design Automation Conf. pages 268-273, 2004.
16. I. Westra. C. Bartels, and P. Groeneveld. Probabilistic congestion prediction. In Proc. Int. Symp on Physical Design, pages 204-209, 2004
17. Z. Xiu, J. D. Ma, S. M. Fowler, and R. A. Rutenbar. Large-scale placement by grid-warping. In Proc. Design Automution Conf., pages 351-356, 2004.
18. X. Yang, B.-K. Choi, and M. Sarrafradeh. Routability-driven white space allocation for fixed-die standard-cell placement. IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, 22(4):410-419, 2003.