Kraftwerk2 - A fast force-directed quadratic placement approach using an accurate net model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 8, 2008, Pages 1398-1411

  Spindler, Peter ^b   Schlichtmann, Ulf ^a,b   Johannes, Frank M ^b  

^a IEEE

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

Bound2Bound; Force directed; Half perimeter wirelength (HPWL); Kraftwerk2; Quadratic placement

Indexed keywords

BENCHMARKING; COMPUTATIONAL EFFICIENCY; CUSTOMER SATISFACTION; PROBLEM SOLVING; QUADRATIC PROGRAMMING; QUALITY ASSURANCE; QUALITY FUNCTION DEPLOYMENT; TOTAL QUALITY MANAGEMENT;

BENCHMARK SUITES; CONVERGENCE (MATHEMATICS); FORCE-DIRECTED; FREE SPACES; HALF-PERIMETER WIRELENGTH (HPWL); HIGH QUALITY (HQ); NET MODELS; QUADRATIC COST FUNCTIONS; QUADRATIC PLACEMENT; RUN TIME; SYSTEMATIC (CO); SYSTEMATIC QUALITY;

QUALITY CONTROL;

EID: 47849103959     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.925783     Document Type: Article

References (44)

1. W.-J. Sun and C. Sechen, "Efficient and effective placement for very large circuits," in Proc. IEEE/ACM ICCAD, 1993, pp. 170-177.
2. J. A. Roy, D. A. Papa, S. N. Adya, H. H. Chan, A. N. Ng, J. F. Lu, and I. L. Markov, "Capo: Robust and scalable open-source min-cut floor-placer," in Proc. ACM/SIGDAISPD, 2005, pp. 224-226.
3. T. Taghavi, X. Yang, and B.-K. Choi, "Dragon2005: Large-scale mixed-size placement tool," in Proc. ACM/SIGDA ISPD, 2005, pp. 245-247.
4. A. R. Agnihorti, S. Ono, C. Li, M. C. Yildiz, A. Khathate, C.-K. Koh, and P. H. Madden, "Mixed block placement via fractional cut recursive bisection," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 5, pp. 748-761, May 2005.
5. W. Naylor, R. Donelly, and L. Sha, "Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer," U.S. Patent 6 301 693, Oct. 9, 2001.
6. A. B. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 5, pp. 734-747, May 2005.
7. T. Chan, J. Cong, and K. Sze, "Multilevel generalized force-directed method for circuit placement," in Proc. ACM/SIGDA ISPD, 2005, pp. 185-192.
8. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "A high-quality mixed-size analytical placer considering preplaced blocks and density constraints," in Proc. IEEE/ACM ICCAD, 2006, pp. 187-192.
9. A. R. Agnihotri and P. H. Madden, "Fast analytic placement using minimum, cost flow," in Proc. Asia South Pacific Des. Autom. Conf., 2007, pp. 128-134.
10. R.-S. Tsay, E. S. Kuh, and C.-P. Hsu, "PROUD: A sea-of-gates placement algorithm," IEEE Des. Test Comput., vol. 5, no. 6, pp. 44-56, Dec. 1988.
11. J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 10, no. 3, pp. 356-365, Mar. 1991.
12. U. Brenner and M. Struzyna, "Faster and better global placement by a new transportation algorithm," in Proc. ACM/IEEE DAC, 2005, pp. 591-596.
13. G.-J. Nam, S. Reda, C. J. Alpert, P. G. Villarrubia, and A. B. Kahng, "A fast hierarchical quadratic placement algorithm," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 4, pp. 678-691, Apr. 2006.
14. B. Hu and M. Marek-Sadowska, "FAR: Fixed-points addition & relaxation based placement," in Proc. ACM/SIGDA ISPD, 2002, pp. 161-166.
15. N. Viswanathan and C C.-N. Chu, "Fastplace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 5, pp. 722-733, May 2005.
16. B. Hu and M. Marek-Sadowska, "Multilevel fixed-point-addition-based VLSI placement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 8, pp. 1188-1203, Aug. 2005.
17. A. Kennings and K. P. Vorwerk, "Force-directed methods for generic placement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 10, pp. 2076-2087, Oct. 2006.
18. N. Viswanathan, G.-J. Nam, C. J. Alpert, P. Villarrubia, H. Ren, and C. Chu, "RQL: Global placement via relaxed quadratic spreading and linearization," in Proc. ACM/IEEE DAC, 2007, pp. 453-458.
19. H. Eisenmann and F. M. Johannes, "Generic global placement and floor-planning," in Proc. ACM/IEEE DAC, Jun. 1998, pp. 269-274.
20. Z. Xiu, J. D. Ma, S. M. Fowler, and R. A. Rutenbar, "Large-scale placement by grid-warping," in Proc. ACM/IEEE DAC, 2004, pp. 351-356.
21. Z. Xiu and R. Rutenbar, "Mixed-size placement with fixed macrocells using grid-warping," in Proc. ACM/SIGDA ISPD, 2007, pp. 103-109.
22. P. Chong and C. Szegedy, "A morphing approach to address placement stability," in Proc. ACM/SIGDA ISPD, 2007, pp. 95-102.
23. P. Spindler and F. M. Johannes, "Fast and robust quadratic placement based on an accurate linear net model," in Proc. IEEE/ACMICCAD, 2006, pp. 179-186.
24. P. Spindler and F. M. Johannes, "Kraftwerk - A fast and robust quadratic placer using an exact linear net model," in Modern Circuit Placement Best Practices and Results, 978th ed. G.-J. Nam and J. Cong, Eds. New York: Springer-Verlag, Sep. 2007, ch. 4, pp. 59-91.
25. G. Sigl, K. Doll, and F. M. Johannes, "Analytical placement: A linear or a quadratic objective function?" inProc. ACM/IEEE DAC, Francisco, CA, 1991, pp. 427-432.
26. J. Vygen, "Algorithms for large-scale flat placement," in Proc. ACM/IEEE DAC, 1997, pp. 746-751.
27. C. Chu, "FLUTE: Fast lookup table based wirelength estimation technique," in Proc. IEEE/ACM ICCAD, 2004, pp. 696-701.
28. K. M. Hall, "An r-dimensional quadratic placement algorithm," Manage. Sci., vol. 17, no. 3, pp. 219-229, Nov. 1970.
29. M. Kowarschik and C. Weiß, "DiMEPACK - A cache-optimized multi-grid library," in Proc. Int. Conf. Parallel Distrib. Process. Techn. Appl., H. Arabnia, Ed., pp. 425-430, Jun. 2001.
30. P. Spindler and F. M. Johannes, "Fast and accurate routing demand estimation for efficient routability-driven placement," in Proc. DATE, Apr. 2007, pp. 1226-1231.
31. B. Obermeier and F. M. Johannes, "Temperature-aware global placement," in Proc. Asia South Pacific Des. Autom. Conf., Yokohama, Japan, Jan. 2004, vol. 1, pp. 143-148.
32. D. Hill, "Method and system for high speed detailed placement of cells within an integrated circuit design," U.S. Patent 6 370 673, Apr. 9, 2002.
33. J. Vygen, "Algorithms for large-scale flat placement," in Proc. ACM/IEEE DAC, 1997, pp. 746-751.
34. J. Cong and M. Xie, "A robust detailed placement for mixed-size IC designs," in Proc. Asia South Pacific Des. Autom. Conf., 2006, pp. 188-194.
35. B. Landman and R. Russo, "On a pin versus block relationship for partitions of logic graphs," IEEE Trans. Comput., vol. C-20, no. 12, pp. 1469-1479, Dec. 1971.
36. S.P.E. Corporation, SPEC CPU 2000. [Online]. Available: http://www. spec.org/cpu2000
37. N. Viswanathan, M. Pan, and C. Chu, "Fastplace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control," in Proc. Asia South Pacific Des. Autom. Conf., 2007, pp. 135-140.
38. G.-J. Nam, C. J. Alpert, P. Villarrubia, B. Winter, and M. Yildiz, "The ISPD2005 placement contest and benchmark suite," in Proc. ACM/SIGDA ISPD, May 2005, pp. 216-219.
39. ISPD 2005 Placement Contest, Mar. 2005. [Online]. Available: http:// www.sigda.org/ispd2005/contest.htm.
40. A. B. Kahng, S. Reda, and Q. Wang, "Architecture and details of a high quality, large-scale analytical placer," in Proc. IEEE/ACM ICCAD, 2005, pp. 890-897.
41. ISPD 2006 Placement Contest, Mar. 2006. [Online]. Available: http://www.sigda.org/ispd2006/contest.html
42. S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and I. L. Markov, "Unification of partitioning, placement and floorplanning," in Proc. IEEE/ACM ICCAD, 2004, pp. 550-557.
43. K. Vorwerk and A. Kennings, "Mixed-size placement via line search," in Proc. IEEE/ACM ICCAD, 2005, pp. 899-904.
44. A. N. Ng, R. Aggarwal, V. Rachmandran, and I. L. Markov, "Solving hard instances of floor placement," in Proc. ISPD, 2006, pp. 170-177.