Nonconvex gate delay modeling and delay optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 9, 2008, Pages 1583-1594

  Tennakoon, Hiran ^a,b   Sechen, Carl ^a,b  

^a IEEE

^b The University of Texas at Dallas   (United States)

Author keywords

Delay modeling; Gate sizing; Nonconvex; Posynomial; Signomial

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURVE FITTING; GATES (TRANSISTOR); LEAST SQUARES APPROXIMATIONS; PROCESS ENGINEERING; WIRELESS NETWORKS;

DELAY MODELING; GATE SIZING; NONCONVEX; POSYNOMIAL; SIGNOMIAL;

OPTIMIZATION;

EID: 50549093705     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.927758     Document Type: Article

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