메뉴 건너뛰기




Volumn 10, Issue 2, 2005, Pages 389-430

Large-scale circuit placement

Author keywords

Large scale optimization; Optimality; Placement; Scalability

Indexed keywords


EID: 30544433363     PISSN: 10844309     EISSN: 10844309     Source Type: Journal    
DOI: 10.1145/1059876.1059886     Document Type: Review
Times cited : (46)

References (105)
  • 8
    • 0001927250 scopus 로고
    • Algebraic multigrid theory: The symmetric case
    • BRANDT, A. 1986. Algebraic multigrid theory: The symmetric case. Appl. Math. Comp. 19, 23-56.
    • (1986) Appl. Math. Comp. , vol.19 , pp. 23-56
    • Brandt, A.1
  • 9
    • 4043106376 scopus 로고    scopus 로고
    • Multigrid solvers and multilevel optimization strategies
    • Kluwer Academic Publishers, Boston, Mass., Chap. 1
    • BRANDT, A. AND RON, D. 2002. Multigrid solvers and multilevel optimization strategies. Multilevel Optimization and VLSICAD. Kluwer Academic Publishers, Boston, Mass., Chap. 1.
    • (2002) Multilevel Optimization and VLSICAD
    • Brandt, A.1    Ron, D.2
  • 11
    • 0037390841 scopus 로고    scopus 로고
    • An effective congestion-driven placement framework
    • BRENNER, U. AND ROHE, A. 2003. An effective congestion-driven placement framework. IEEE Trans. CAD 22, 4 (Apr.), 387-394.
    • (2003) IEEE Trans. CAD , vol.22 , Issue.4 APR , pp. 387-394
    • Brenner, U.1    Rohe, A.2
  • 16
    • 0346237588 scopus 로고    scopus 로고
    • compiled on 10/25/1999. Envisia ultra placer reference
    • CADENCE DESIGN SYSTEMS, INC. 1999. QPlace version 5.1.55, compiled on 10/25/1999. Envisia ultra placer reference.
    • (1999) QPlace Version 5.1.55
  • 19
    • 0034544638 scopus 로고    scopus 로고
    • Iterative partitioning with varying node weights
    • CALDWELL, A., KAHNG, A., AND MARKOV, I. 2000c. Iterative partitioning with varying node weights. VLSI Design II, 3, 249-258.
    • (2000) VLSI Design II , vol.3 , pp. 249-258
    • Caldwell, A.1    Kahng, A.2    Markov, I.3
  • 20
    • 0034313430 scopus 로고    scopus 로고
    • Optimal partitioners and end-case placers for standard-cell layout
    • CALDWELL, A., KAHNG, A., AND MARKOV, I. 2000d. Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. on CAD 19, 11, 1304-1314.
    • (2000) IEEE Trans. on CAD , vol.19 , Issue.11 , pp. 1304-1314
    • Caldwell, A.1    Kahng, A.2    Markov, I.3
  • 25
    • 0037387778 scopus 로고    scopus 로고
    • Multilevel global placement with congestion control
    • CHANG, C.-C., CONG, J., PAN, D., AND YUAN, X. 2003a. Multilevel global placement with congestion control. IEEE Trans. CAD 22, 4 (Apr.), 395-409.
    • (2003) IEEE Trans. CAD , vol.22 , Issue.4 APR , pp. 395-409
    • Chang, C.-C.1    Cong, J.2    Pan, D.3    Yuan, X.4
  • 30
    • 0021455306 scopus 로고
    • Module placement based on resistive network optimization
    • CHENG, C. AND KUH, E. 1984. Module placement based on resistive network optimization. IEEE Trans. CAD. CAD-3, 3.
    • (1984) IEEE Trans. CAD , vol.CAD-3 , pp. 3
    • Cheng, C.1    Kuh, E.2
  • 32
    • 2942639682 scopus 로고    scopus 로고
    • FastPlace: Efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model
    • CHU, C. AND VISWANATHAN, N. 2004. FastPlace: Efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. In Proceedings of the International Symposium on Physical Design (Apr.). 26-33.
    • (2004) Proceedings of the International Symposium on Physical Design , Issue.APR , pp. 26-33
    • Chu, C.1    Viswanathan, N.2
  • 33
    • 0000090413 scopus 로고    scopus 로고
    • An interconnect-centric design flow for nanometer technologies
    • CONG, J. 2001. An interconnect-centric design flow for nanometer technologies. Proc. IEEE 89, 4 (Apr.), 505-527.
    • (2001) Proc. IEEE , vol.89 , Issue.4 APR , pp. 505-527
    • Cong, J.1
  • 34
    • 0003132154 scopus 로고    scopus 로고
    • Edge separability based circuit clustering with application to circuit partitioning
    • Yokohama Japan
    • CONG, J. AND LIM, S. 2000. Edge separability based circuit clustering with application to circuit partitioning. In Proceedings of the Asia South Pacific Design Automation Conference (Yokohama Japan). 429-434.
    • (2000) Proceedings of the Asia South Pacific Design Automation Conference , pp. 429-434
    • Cong, J.1    Lim, S.2
  • 37
    • 0348040120 scopus 로고    scopus 로고
    • Optimality and stability of timing-driven placement algorithms
    • (San Jose, Calif.). IEEE Computer Society Press, Los Alamitos, Calif
    • CONG, J., ROMESIS, M., AND XIE, M. Nov 2003a. Optimality and stability of timing-driven placement algorithms. In Proceedings of the IEEE International Conference on Computer Aided Design. (San Jose, Calif.). IEEE Computer Society Press, Los Alamitos, Calif.
    • (2003) Proceedings of the IEEE International Conference on Computer Aided Design
    • Cong, J.1    Romesis, M.2    Nov, X.M.3
  • 40
    • 0021784846 scopus 로고
    • A procedure for placement of standard-cell VLSI circuits
    • DUNLOP, A. AND KERNIGHAN, B. 1985. A procedure for placement of standard-cell VLSI circuits. IEEE Trans. CAD. CAD-4, 1 (Jan.).
    • (1985) IEEE Trans. CAD , vol.CAD-4 , Issue.1 JAN
    • Dunlop, A.1    Kernighan, B.2
  • 43
    • 29144519019 scopus 로고    scopus 로고
    • American Mathematical Society, Providence, R. I.
    • EVANS, L. C. 2002. Partial Diferential Equations. American Mathematical Society, Providence, R. I.
    • (2002) Partial Diferential Equations
    • Evans, L.C.1
  • 47
    • 0019478261 scopus 로고
    • An efficient algorithm for the two-dimensional placement problem in electrical circuit layout
    • GOTO, S. 1981. An efficient algorithm for the two-dimensional placement problem in electrical circuit layout. IEEE Trans. Circuits and Systems 28, 1 (Jan.), 12-18.
    • (1981) IEEE Trans. Circuits and Systems , vol.28 , Issue.1 JAN , pp. 12-18
    • Goto, S.1
  • 48
    • 0012051942 scopus 로고    scopus 로고
    • On implementation choices for iterative improvement partitioning algorithms
    • HAGEN, L., HUANG, J. H., AND KAHNG, A. B. 1997. On implementation choices for iterative improvement partitioning algorithms. IEEE Trans. CAD 16, 10, 1199-1205.
    • (1997) IEEE Trans. CAD , vol.16 , Issue.10 , pp. 1199-1205
    • Hagen, L.1    Huang, J.H.2    Kahng, A.B.3
  • 51
    • 0027316516 scopus 로고
    • Prime: A timing-driven placement tool using a piecewise linear resistive network approach
    • ACM, New York
    • HAMADA, T., CHENG, C. K., AND CHAU, P. M. 1993. Prime: A timing-driven placement tool using a piecewise linear resistive network approach. In Proceedings of the ACM/IEEE Design Automation Conference. ACM, New York, 531-536.
    • (1993) Proceedings of the ACM/IEEE Design Automation Conference , pp. 531-536
    • Hamada, T.1    Cheng, C.K.2    Chau, P.M.3
  • 55
    • 2342433436 scopus 로고    scopus 로고
    • Fine granularity clustering based placement
    • HU, B. AND MAREK-SADOWSKA, M. 2004. Fine granularity clustering based placement. IEEE Trans. CAD 23, 1264-1276.
    • (2004) IEEE Trans. CAD , vol.23 , pp. 1264-1276
    • Hu, B.1    Marek-Sadowska, M.2
  • 56
    • 0034478056 scopus 로고    scopus 로고
    • Mongrel: Hybrid techniques for standard-cell placement
    • (San Jose, Calif., Nov.). IEEE Computer Society Press, Los Alamitos, Calif
    • HUR, S.-W. AND LILLIS, J. 2000. Mongrel: Hybrid techniques for standard-cell placement. In Proceedings of the IEEE International Conference on Computer-Aided Design (San Jose, Calif., Nov.). IEEE Computer Society Press, Los Alamitos, Calif., 165-170.
    • (2000) Proceedings of the IEEE International Conference on Computer-Aided Design , pp. 165-170
    • Hur, S.-W.1    Lillis, J.2
  • 58
    • 4444341110 scopus 로고    scopus 로고
    • Placement feedback: A concept and method for better min-cut placements
    • ACM, New York
    • KAHNG, A. AND REDA, S. 2004. Placement feedback: A concept and method for better min-cut placements. In Proceedings of ACM/IEEE Design Automation Conference. ACM, New York, 357-362.
    • (2004) Proceedings of ACM/IEEE Design Automation Conference , pp. 357-362
    • Kahng, A.1    Reda, S.2
  • 60
    • 0347498980 scopus 로고    scopus 로고
    • Multilevel algorithms for multi-constraint hypergraph partitioning
    • Department of Computer Science, University of Minnesota, Minneapolis, Minn
    • KARYPIS, G. 1999. Multilevel algorithms for multi-constraint hypergraph partitioning. Tech. Rep. 99-034, Department of Computer Science, University of Minnesota, Minneapolis, Minn.
    • (1999) Tech. Rep. 99-034
    • Karypis, G.1
  • 61
    • 4644318330 scopus 로고    scopus 로고
    • Multilevel hypergraph partitioning
    • Kluwer Academic Publishers, Boston, Mass., Chap. 3
    • KARYPIS, G. 2003. Multilevel hypergraph partitioning. Multilevel Optimization and VLSICAD. Kluwer Academic Publishers, Boston, Mass., Chap. 3.
    • (2003) Multilevel Optimization and VLSICAD
    • Karypis, G.1
  • 63
    • 0026131224 scopus 로고
    • Gordian: VLSI placement by quadratic programming and slicing optimization
    • KLEINHANS, J., SIGL, G., JOHANNES, F., AND ANTREICH, K. 1991. Gordian: VLSI placement by quadratic programming and slicing optimization. IEEE Trans. CAD CAD-10, 356-365.
    • (1991) IEEE Trans. CAD , vol.CAD-10 , pp. 356-365
    • Kleinhans, J.1    Sigl, G.2    Johannes, F.3    Antreich, K.4
  • 65
    • 2942649186 scopus 로고    scopus 로고
    • On improving recursive bipartitioning-based placement
    • Purdue University
    • LI, C. AND KOH, C.-K. 2003. On improving recursive bipartitioning-based placement. Tech. Rep. TR-ECE 03-14, Purdue University.
    • (2003) Tech. Rep. TR-ECE 03-14
    • Li, C.1    Koh, C.-K.2
  • 67
    • 0036179948 scopus 로고    scopus 로고
    • Estimating routing congestion using probabilistic analysis
    • LOU, J., THAKUB, S., KRISHNAMOORTHY, S., AND SHENG, H. 2002. Estimating routing congestion using probabilistic analysis. IEEE Trans. CAD 21, 1 (Jan.), 32-41.
    • (2002) IEEE Trans. CAD , vol.21 , Issue.1 JAN , pp. 32-41
    • Lou, J.1    Thakub, S.2    Krishnamoorthy, S.3    Sheng, H.4
  • 68
    • 0026175521 scopus 로고
    • A fast physical constraint generator for timing driven layout
    • ACM, New York
    • LUK, W. K. 1991. A fast physical constraint generator for timing driven layout. In Proceedings of the ACM/IEEE Design Automation Conference. ACM, New York, 626-631.
    • (1991) Proceedings of the ACM/IEEE Design Automation Conference , pp. 626-631
    • Luk, W.K.1
  • 77
    • 0018480537 scopus 로고
    • A force-directed component placement procedure for printed circuit boards
    • QUINN, N. AND BREUER, M. 1979. A force-directed component placement procedure for printed circuit boards. IEEE Trans. Circ Syst CAS CAS-26, 377-388.
    • (1979) IEEE Trans. Circ Syst CAS , vol.CAS-26 , pp. 377-388
    • Quinn, N.1    Breuer, M.2
  • 81
    • 0032640531 scopus 로고    scopus 로고
    • Trading quality for compile time: Ultra-fast placement for FPGAs
    • ACM, New York
    • SANKAR, Y. AND ROSE, J. 1999. Trading quality for compile time: Ultra-fast placement for FPGAs. In FPGA99, ACM Symposium on FPGAs. ACM, New York, 157-166.
    • (1999) FPGA99, ACM Symposium on FPGAs , pp. 157-166
    • Sankar, Y.1    Rose, J.2
  • 82
    • 0031273491 scopus 로고    scopus 로고
    • A delay budgeting algorithm ensuring maximum flexibility in placement
    • SARRAFZADEH, M., KNOL, D. A., AND TELLEZ, G. E. 1997a. A delay budgeting algorithm ensuring maximum flexibility in placement. IEEE Trans. CAD of Integ. Circ. Syst. 16, 11, 1332-1341.
    • (1997) IEEE Trans. CAD of Integ. Circ. Syst. , vol.16 , Issue.11 , pp. 1332-1341
    • Sarrafzadeh, M.1    Knol, D.A.2    Tellez, G.E.3
  • 90
    • 0024125597 scopus 로고
    • Proud: A fast sea-of-gates placement algorithm
    • TSAY, R., KUH, E., AND HSU, C. 1988. Proud: A fast sea-of-gates placement algorithm. IEEE Desi. Test Comput. 44-56.
    • (1988) IEEE Desi. Test Comput. , pp. 44-56
    • Tsay, R.1    Kuh, E.2    Hsu, C.3
  • 91
    • 0026175786 scopus 로고
    • An analytic net weighting approach for performance optimization in circuit placement
    • ACM, New York
    • TSAY, R. S. AND KOEHL, J. 1991. An analytic net weighting approach for performance optimization in circuit placement. In Proceedings of the ACMI IEEE Design Automation Conference. ACM, New York, 620-625.
    • (1991) Proceedings of the ACMI IEEE Design Automation Conference , pp. 620-625
    • Tsay, R.S.1    Koehl, J.2
  • 94
    • 30544441444 scopus 로고    scopus 로고
    • Report 00900-OR, Research Institute for Discrete Mathematics, University of Bonn, Bonn, Germany
    • VYGEN, J. 2000. Four-way partitioning of two-dimensional sets. Report 00900-OR, Research Institute for Discrete Mathematics, University of Bonn, Bonn, Germany.
    • (2000) Four-way Partitioning of Two-dimensional Sets
    • Vygen, J.1
  • 100
    • 0037387687 scopus 로고    scopus 로고
    • Routability-driven white space allocation for fixed-die standard-cell placement
    • YANG, X., CHOI, B., AND SARRAFZADEH, M. 2003. Routability-driven white space allocation for fixed-die standard-cell placement. IEEE Trans, CAD 22, 4 (Apr.), 410-419.
    • (2003) IEEE Trans, CAD , vol.22 , Issue.4 APR , pp. 410-419
    • Yang, X.1    Choi, B.2    Sarrafzadeh, M.3
  • 101
    • 0036182929 scopus 로고    scopus 로고
    • Congestion estimation during top-down placement
    • YANG, X., KASTNER, R., AND SAKRAFZADEH, M. 2002b. Congestion estimation during top-down placement. IEEE Trans. CAD 21, 1 (Jan.), 72-80.
    • (2002) IEEE Trans. CAD , vol.21 , Issue.1 JAN , pp. 72-80
    • Yang, X.1    Kastner, R.2    Sakrafzadeh, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.