Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 167-172

  Jiang, Zhe Wei ^a   Su, Bor Yiing ^b   Chang, Yao Wen ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b Department of Electrical Engineering and Computer Science ^*  (United States)

Author keywords

Physical design; Placement; Routability

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER NETWORKS; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; MARINE BIOLOGY; METAL RECOVERY; MULTIPROCESSING SYSTEMS; OPTIMIZATION;

PHYSICAL DESIGN; PLACEMENT; ROUTABILITY;

ROUTING ALGORITHMS;

EID: 51549118747     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555802     Document Type: Conference Paper

References (20)

1. ISPD 2005 Placement Contest. http://www.sigda.org/ispd2005/contest.htm.
2. ISPD 2007 Routing Contest. http://www.sigda.org/ispd2007/contest.html.
3. Labyrinth Format. http://www.ece.ucsb.edu/̃ kastner/labyrinth/.
4. T. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie. mPL6: Enhanced multilevel mixed-size placement. In Proc. of ISPD, pages 212-214, San Jose, California, USA, 2006.
5. T. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In Proc. of ISPD, pages 185-192, San Francisco, California, USA, 2005.
6. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. In Proc. of ICCAD, pages 187-192, San Jose, California, USA, 2006.
7. H. Eisenmann and F. M. Johannes. Generic global placement and floorplanning. In Proc. of DAC, pages 269-274, San Francisco, California, USA, 1998.
8. J. R. Gao, P. C. Wu, and T. C. Wang. A new global router for modern designs. In Proc. of ASPDAC, pages 232-237, Seoul, Korea, 2008.
9. A. B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. IEEE Trans. on CAD, 24(5), 2005.
10. A. B. Kahng and Q. Wang. A faster implementation of APlace. In Proc. of ISPD, pages 218-220, San Jose, California, USA, 2006.
11. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. Gordian: VLSI placement by quadratic programming and slicing optimization. IEEE Trans. on CAD, 10(3):356-365, 1991.
12. C. Li, M. Xie, C.-K. Koh, J. Cong, and P. H. Madden. Routability-driven placement and white space allocation. In Proc. of ICCAD, pages 394-401, San Jose, Carlifornia, USA, 2004.
13. J. Lou, S. Thakur, S. Krishnamoorthy, and H. S. Sheng. Estimating routing congestion using probabilistic analysis. IEEE Trans. on CAD, 21(1):32-41, 2002.
14. D. R. Naylor, W. C. and L. Sha. US patent 6,301,693: Non-linear optimization system and method for wire length and dealy optimization for an automatic electric circuit placer. 2001.
15. M. Pan and C. Chu. FastRoute 2.0: A high-quality and efficient global router. In Proc. of ASPDAC, pages 250-255, Yokohama, Japan, 2007.
16. M. Pan and C. Chu. IPR: An integrated placement and routing algorithm. In Proc. of DAC, pages 59-62, San Diego, California, USA, 2007.
17. J. A. Roy, J. F. Lu, and I. L. Markov. Seeing the forest and the trees: Steiner wirelength optimization in placement. IEEE Trans. of CAD, 26(4):632-644, 2007.
18. P. Spindler and F. M. Johannes. Fast and accurate routing demand estimation for efficient routability-driven placement. In Proc. of DATE, pages 1226-1231, Nice, France, 2007.
19. X. Yang, B.-K. Choi, and M. Sarrafzadeh. Routability-driven white space allocation for fixed-die standard-cell placement. In Proc. of ISPD, pages 42-47, San Diego, California, USA, 2002.
20. X. Yang, R. Kastner, and M. Sarrafzadeh. Congestion estimation during top-down placement. IEEE Trans. on CAD, 21(1):72-80, 2002.