Efficient timing closure without timing driven placement and routing

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 268-273

  Vujkovic, Miodrag ^a   Wadkins, David ^a   Swartz, Bill ^b   Sechen, Carl ^a  

^a University of Washington   (United States)

^b InternetCADcom Inc   (United States)

Author keywords

Digital design flow; Gate sizing; Placement and routing; Timing closure

Indexed keywords

ALGORITHMS; BENCHMARKING; DESIGN AIDS; ITERATIVE METHODS; MICROPROCESSOR CHIPS; OPTIMIZATION; ROUTERS; TREES (MATHEMATICS);

DIGITAL DESIGN FLOW; GATE SIZING; PLACEMENT AND ROUTING; TIMING CLOSURE;

INTEGRATED CIRCUITS;

EID: 4444239809     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996646     Document Type: Conference Paper

References (11)

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