Keeping hot chips cool

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 285-288

  Puri, Ruchir ^a   Stok, Leon ^b   Bhattacharya, Subhrajit ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

High Performance; Low power; VLSI Design

Indexed keywords

ELECTRIC CLOCKS; ELECTRIC POTENTIAL; ENERGY DISSIPATION; ENERGY UTILIZATION; LEAKAGE CURRENTS; PRODUCT DESIGN;

HIGH-PERFORMANCE; LOW POWER; VLSI DESIGN;

CMOS INTEGRATED CIRCUITS;

EID: 27944450083     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193818     Document Type: Conference Paper

References (10)

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2. Puri, R. et al, Pushing ASIC performance in a power envelope, DAC 2003.
3. Kosonocky, S. et al, Low Power Circuits and Technlogy for wireless digital systems, IBM Journal of R&D, Vol. 47, No. 2/3, 2003.
4. Puri, R., et al., Minimizing power with Flexible Voltage Islands, ISCAS 2005.
5. Nassif, S., Delay Variability: Sources, Impact and Trends, ISSCC, 2000.
6. Warnock, J., "Circuit Design with Leaky Transistor", ISSCC Workshop on Design in power constrainted era, 2003.
7. Lackey, D. et al, "Managing power & performance for SoC Designs using Voltage Islands", ICCAD 2002.
8. Kim, S. et al., Understanding and minimizing ground bounce during mode transition of power gating structures., ISLPED 2003.
9. Keshavarzi, A et al, Effectiveness of reverse body biasing for scaled technologies, ISLPED 2001.
10. Roy, K., Clcok Gating for Microprocessor power reduction, High Performance Computer Architecture Symposium, 2003.