Congestion minimization during placement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 10, 2000, Pages 1140-1148

  Wang, Maogang ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COST BENEFIT ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; TREES (MATHEMATICS); VLSI CIRCUITS;

CONGESTION MINIMIZATION; STEINER TREES; WIRELENGTH;

INTEGRATED CIRCUIT TESTING;

EID: 0034296451     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.875296     Document Type: Article

References (16)

1. A. E. Dunlop and B. W. Kernighan, "A procedure for placement of standard cell VLSI circuits," IEEE Trans. Computer Aided Design, vol. 4, pp. 92-98, Jan. 1985.
2. H. Eisenmann and F. M. Johannes, "Generic global placement and floor-planning," in Proc. Design Automation Conf., 1998, pp. 269-274.
3. L. R. Ford and D. R. Fulkerson, Flows in Network. Princeton, NJ: Princeton Univ. Press, 1962.
4. D. Huang and A. B. Kahng, "Partitioning-based standard-cell global placement with an exact objective," in Proc. Int. Symp. Physical Design, Apr. 1997, pp. 18-25.
5. J. M. Klainhans, G. Sigl, F. M. Johannes, and K. J. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization," IEEE Trans. Computer Aided Design, vol. 10, pp. 365-372, Mar. 1991.
6. T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. New York: Wiley, 1990.
7. G. Meixner and U. Lauther, "Congestion-driven placement using a new multi-partitioning heuristic," in Proc. Int. Conf. Computer-Aided Design, Nov. 1990, pp. 332-335.
8. P. N. Parakh, R. B. Brown, and K. A. Sakallah, "Congestion driven quadratic placement," in Proc. Design Automation Conf., 1998, pp. 275-278.
9. Saab96, "A fast clustering-based Min-cut placement algorithm with simulated-annealing performance," VLSI Design: Int. J. Custom-Chip Design, Simulation, Testing, vol. 5, no. 1, pp. 37-48, 1996.
10. M. Sarrafzadeh and M. Wang, "NRG: Global and detailed placement," in Proc. Int. Conf. Computer-Aided Design, pp. 532-537.
11. M. Wang and M. Sarrafzadeh, "Interaction among cost functions in placement," in Proc. Int. Conf. VLSI and CAD, 1999.
12. C. Sechen, VLSI placement and global routing using simulated annealing, B. V. Deventer, Ed, The Netherlands: Kluwer, 1988.
13. K. Shahookar and P. Mazumder, "VLSI cell placement techniques," ACM Computing Surveys, vol. 23, no. 2, pp. 143-220, June 1991.
14. P. R. Suaris and G. Kedem, "Quadrisection: A new approach to standard cell layout," in Proc. Design Automation Conf., 1987, pp. 474-477.
15. R. S. Tsay, E. S. Kuh, and C. P. Hsu, "PROUD: A sea-of-gates placement algorithm," IEEE Design Test Comput., pp. 44-56, Dec. 1988.
16. M. Wang and M. Sarrafzadeh, "On behavior of congestion minimization during placement," in Proc. Int. Symp. Physical Design, Apr. 1990, pp. 145-150.