TSV-aware analytical placement for 3D IC designs

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 664-669

  Hsu, Meng Kai ^a   Chang, Yao Wen ^a   Balabanov, Valeriy ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

3D ICs; Physical Design; Placement

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRONICS PACKAGING; TIMING CIRCUITS;

3-D ICS; ANALYTICAL PLACEMENT; CRITICAL CHALLENGES; PHYSICAL DESIGN; PLACEMENT; THREE DIMENSIONAL INTEGRATED CIRCUITS (3-D IC); THROUGH SILICON VIAS; TRANSMITTING SIGNAL;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 80052663262     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024875     Document Type: Conference Paper

References (19)

1. Cadence. SoC Encounter. http://www.cadence.com.
2. IBM-PLACE Benchmarks. http://er.cs.ucla.edu/benchmarks/ibm-place.
3. IWLS 2005 Benchmarks. http://iwls.org/iwls2005/benchmarks.html.
4. T. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie. mPL6: Enhanced multilevel mixed-size placement. In Proc. of ISPD, 2006.
5. T. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In Proc. of ISPD, 2005.
6. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE Trans. on CAD, 27(7), 2008.
7. J. Cong and G. Luo. A multilevel analytical placement for 3D ICs. In Proc. of ASPDAC, 2009.
8. J. Cong and G. Luo. An analytical placer for mixed-size 3D placement. In Proc. of ISPD, 2010.
9. J. Cong, G. Luo, J. Wei, and Y. Zhang. Thermal-aware 3D IC placement via transformation. In Proc. of ASPDAC, 2007.
10. B. Goplen and S. Sapatnekar. Efficient thermal placement of standard cells in 3D ICs using a force directed approach. In Proc. of ICCAD, 2003.
11. B. Goplen and S. Sapatnekar. Placement of 3D ICs with thermal and interlayer via considerations. In Proc. of DAC, 2007.
12. D. Hill. US patent 6,370,673: Method and system for high speed detailed placement of cells within an intergrated circuit design. 2002.
13. A. B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. IEEE Trans. on CAD, 24(5), May 2005.
14. A. B. Kahng and Q. Wang. A faster implementation of APlace. In Proc. of ISPD, 2006.
15. D. H. Kim, K. Athikulwongse, and S. K. Lim. A study of through-silicon-via impact on the 3D stacked IC layout. In Proc. of ICCAD, 2009.
16. W. C. Naylor, R. Donelly, and L. Sha. US patent 6,301,693: Non-linear optimization system and method for wire length and dealy optimization for an automatic electric circuit placer. 2001.
17. P. Spindler, U. Schlichtmann, and F. M. Johannes. Abacus: fast legalization of standard cell circuits with minimal movement. In Proc. of ISPD, 2008.
18. L.-T. Wang, Y.-W. Chang, and K.-T. Cheng. Electronic Design Automation: Synthesis, Verication, and Test (Systmes on Silicon). Morgan Kaufmann, 2009.
19. H. Zhou. Efficient Steiner tree construction based on spanning graphs. In Proc. of ISPD, 2003.