Optimizing nonmonotonic interconnect using functional simulation and logic restructuring

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 12, 2008, Pages 2107-2119

  Plaza, Stephen M ^a   Markov, Igor L ^a   Bertacco, Valeria M ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Logic simulation; Logic synthesis; Physical synthesis

Indexed keywords

CODES (SYMBOLS); DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS;

AREA OVERHEADS; DELAY ESTIMATIONS; DESIGN OPTIMIZATIONS; FUNCTIONAL SIMULATIONS; INTER-CONNECTS; INTERCONNECT DELAYS; INTERCONNECT REDUCTIONS; LOGIC RESTRUCTURING; LOGIC SIMULATION; LOGIC SIMULATIONS; LOGIC SYNTHESES; LOGIC SYNTHESIS; MONOTONICITY; NEW APPROACHES; NONMONOTONIC; NOVEL CRITERIONS; PERFORMANCE OBJECTIVES; PHYSICAL DOMAINS; PHYSICAL SYNTHESES; PHYSICAL SYNTHESIS; SYNTHESIS ALGORITHMS; WIRE LENGTHS;

OPTIMIZATION;

EID: 56749130513     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2006156     Document Type: Conference Paper

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