Constraint graph-based macro placement for modern mixed-size circuit designs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 218-223

  Chen, Hsin Chen ^a   Chuang, Yi Lin ^a   Chang, Yao Wen ^a   Chang, Yung Chung ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b Genesys Logic Inc   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL GEOMETRY; COMPUTER AIDED DESIGN; DESIGN; INTEGRATED CIRCUIT MANUFACTURE; LINEARIZATION; PLACERS;

CHIP BOUNDARIES; CIRCUIT DESIGNS; CONSTRAINT GRAPHS; COST EVALUATIONS; HIGH QUALITIES; MACRO PLACEMENTS; SOLUTION QUALITIES; UTILIZATION RATES;

MACROS;

EID: 57849099197     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681577     Document Type: Conference Paper

References (19)

1. ISPD 2006 Program, http://www.ispd.cc/program.html.
2. S. N. Adya and I. L. Markov. Combinatorial techniques for mixed-size placement. ACM TODAES, 10(5), pages 58-90, January 2005.
3. E. Wein and J. Benkoski. Hard macros will revolutionize SoC design. EETimes Online, August 2004.
4. A. R. Agnihotri, S. Ono, and P. H. Madden. Recursive bisection placement: Feng Shui 5.0 implementation details. In Proc. ISPD, pages 230-232, April 2005.
5. T. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie. mPL6: Enhanced multilevel mixed-size placement. In Proc. ISPD, pages 212-214, April 2006.
6. C-C. Chang, J. Cong, and X. Yuan. Multi-level placement for large-scale mixed-size IC designs. In Proc. ASP-DAC, pages 325-330, January 2003.
7. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. A high quality analytical placer considering preplaced blocks and density constraint. In Proc. ICCAD, pages 187-192, November 2006.
8. -. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE TCAD, 27(7), pages 1228-1240, July 2008.
9. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Liu, and D. Liu. MP-trees: A. packing-based macro placement algorithm for mixed-size designs. In Proc. DAC, pages 447-452, June 2007.
10. -. MP-trees: A packing-based macro placement algorithm for modern mixed-size designs. IEEE TCAD, 27(9), September 2008.
11. J. Cong, M. Romesis, and J. R. Shinnerl. Fast floorplanning by lookahead enabled recursive bipartitioning. In Proc. ASPDAC, pages 1119-1122, January 2005.
12. J. Cong and M. Xie. A robust detailed placement for mixed-size ic designs. In Proc. ASP-DAC, pages 188-194, January 2006.
13. A. B. Kahng and Q. Wang. A faster implementation of APlace. In Proc. ISPD, pages 218-220, April 2006.
14. J.-M. Lin and Y.-W. Chang. TCG: A transitive closure graph-based representation for non-slicing floorplans. In Proc. DAC, pages 764769, June 2001.
15. -. TCG: A transitive closure graph based representation for general floorplans. IEEE Trans. VLSI Systems, pages 288-292, February 2005.
16. M. D. Moffitt, A. N. Ng, I. L. Markov, and M. E. Pollack. Constraint driven floorplan repair. In Proc. DAC, pages 1103-1108, July 2006.
17. B. Obermeier, H. Ranke, and F. M. Johannes. Kraftwerk: a versatile placement approach. In Proc. ISPD, pages 242-244, April 2005.
18. J. Roy, D. Papa, A. Ng, and I. Markov. Satisfying whitespace requirements in top-down placement. In Proc. ISPD, pages 206-208, April 2006.
19. T. Taghavi, X. Yang, B.-K. Choi, M. Wang, and M. Sarrafzadeh. Dragon2006: Blockage-aware congestion-controlling mixedsize placer. In Proc. ISPD, pages 209-211, April 2006.