On whitespace and stability in physical synthesis

Integration, the VLSI Journal

Volumn 39, Issue 4, 2006, Pages 340-362

  Adya, Saurabh N ^a   Markov, Igor L ^b   Villarrubia, Paul G ^c  

^a Synplicity Inc   (United States)

^b The Department of Civil and Environmental Engineering   (United States)

^c IBM   (United States)

Author keywords

Congestion; Layout; Placement; Resizing; Routing; Signal delay; Timing; Utilization; VLSI; Wirelength

Indexed keywords

ALGORITHMS; CONGESTION CONTROL (COMMUNICATION); CONVERGENCE OF NUMERICAL METHODS; GATES (TRANSISTOR); NETWORK PROTOCOLS; PROBLEM SOLVING;

CONGESTION; LAYOUT; PLACEMENT; RESIZING; ROUTING; SIGNAL DELAY; TIMING; UTILIZATION; WIRELENGTH;

VLSI CIRCUITS;

EID: 33646496133     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2005.08.003     Document Type: Article

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