CRISP: Congestion reduction by iterated spreading during placement

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 357-362

  Roy, Jarrod A ^a,b   Viswanathan, Natarajan ^b   Nam, Gi Joon ^b   Alpert, Charles J ^b   Markov, Igor L ^a  

^a University of Michigan   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA UTILIZATION; COMMERCIAL DESIGN; COMMERCIAL TOOLS; CONGESTION REDUCTION; DETAILED ROUTING; DIE AREA; FLOORPLANS; GLOBAL ROUTING; JOINT OPTIMIZATION; PLACEMENT AND ROUTING; ROUTE OPTIMIZATION; RUNTIMES; STANDARD CELL;

COMPUTER AIDED DESIGN; ELECTRIC BATTERIES; SIGNAL PROCESSING;

TRAFFIC CONGESTION;

EID: 76349116486     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. C. J. Alpert, D. P. Mehta and S. S. Sapatnekar, eds., Handbook of Algorithms for VLSI Physical Design Automation, CRC Press, 2008.
2. U. Brenner and A. Rohe, "An Effective Congestion Driven Placement Framework," ISPD 2002, pp. 6-11.
3. T. F. Chan, J. Cong, J. Shinnerl, K. Sze and M. Xie, "mPL6: Enhanced Multilevel Mixed-size Placement with Congestion Control," Modern Circuit Placement, eds. G.-J. Nam and J. Cong, Springer, pp. 247-288, 2007.
4. Y.-J. Chang, Y.-T. Lee and T.-C. Wang, "NTHU-Route 2.0: A fast and stable global router," ICCAD 2008, pp. 338-343.
5. C. C. N. Chu and M. Pan, "IPR: An Integrated Placement and Routing Algorithm," DAC 2007, pp. 59-62.
6. C. C. N. Chu and Y.-C. Wong, "FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design," IEEE TCAD 27(1), pp. 70-83, 2008.
7. Z.-W. Jiang, B.-Y. Su and Y.-W. Chang, "Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs," DAC 2008, pp. 167-172.
8. C. Li, M. Xie, C.-K. Koh, J. Cong and P. H. Madden, "Routability- driven Placement and White Space Allocation," IEEE TCAD 26(5), pp. 858-871, 2007.
9. G.-J. Nam, C. C. N. Sze and M. Can Yildiz, "The ISPD global routing benchmark suite," ISPD 2008, pp. 156-159.
10. N. Selvakkumaran, P. N. Parakh and G. Karypis, "Perimeter-degree: A Priori Metric for Directly Measuring and Homogenizing Interconnection Complexity in Multilevel Placement," SLIP 2003, pp. 53-59.
11. P. Spindler and F. M. Johannes, "Fast and accurate routing demand estimation for efficient routability-driven placement," DATE 2007, pp. 1226-1231
12. K. Tsota, C.-K. Koh and V. Balakrishnan, "Guiding Global Placement with Wire Density," ICCAD 2008, pp. 212-217.
13. N. Viswanathan, M. Pan and C. C. N. Chu "FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control," ASP-DAC 2007, pp. 135-140.
14. X. Yang, R. Kastner and M. Sarrafzadeh, "Congestion Estimation During Top-down Placement," IEEE TCAD 21(1), pp. 72-80, 2002.