Detailed placement with net length constraints

Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Volumn , Issue , 2003, Pages 22-27

  Halpin, B ^a   Sehgal, N ^b   Chen, C Y R ^a  

^a SYRACUSE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Automatic control; Circuit simulation; Constraint optimization; Delay; Design engineering; Optimization methods; Simulated annealing; Timing; Transportation; Very large scale integration

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATION; CIRCUIT SIMULATION; CONSTRAINED OPTIMIZATION; CONTROL; MICROPROCESSOR CHIPS; PLACERS; PROGRAMMABLE LOGIC CONTROLLERS; SIMULATED ANNEALING; SYSTEM-ON-CHIP; TRANSPORTATION; VLSI CIRCUITS;

CONSTRAINT OPTIMIZATIONS; DELAY; DESIGN ENGINEERING; OPTIMIZATION METHOD; TIMING;

TIMING CIRCUITS;

EID: 84872332616     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWSOC.2003.1212999     Document Type: Conference Paper

References (11)

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