Multi-level placement for large-scale mixed-size IC designs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 325-330

  Chang, Chin Chih ^a,b   Cong, J ^a   Yuan, Xin ^a  

^a University of California   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; OPTIMIZATION;

MIXED SIZE; MIXED-SIZE PLACEMENT; MULTILEVEL OPTIMIZATION; MULTILEVELS; SIZE VARIATION; STANDARD-CELL PLACEMENT; WIRE LENGTH; WIRELENGTH MINIMIZATION;

DESIGN;

EID: 84954416950     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195036     Document Type: Conference Paper

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