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Volumn , Issue , 2002, Pages 172-176

A novel net weighting algorithm for timing-driven placement

Author keywords

[No Author keywords available]

Indexed keywords

COUNTING ALGORITHM; DIRECTED ACYCLIC GRAPH; NET WEIGHTING ALGORITHMS; PATH DELAY REDUCTION; TIMING DRIVEN PLACEMENT;

EID: 0036907067     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774597     Document Type: Conference Paper
Times cited : (93)

References (13)
  • 2
    • 0027316516 scopus 로고
    • Prime: A timing-driven placement tool using a piecewise linear resistive network approach
    • T. Hamada, C. K. Cheng, and P. M. Chau, "Prime: a timing-driven placement tool using a piecewise linear resistive network approach," in Proc. ACM/IEEE Design Automation Conference, pp. 531-536, 1993.
    • (1993) Proc. ACM/IEEE Design Automation Conference , pp. 531-536
    • Hamada, T.1    Cheng, C.K.2    Chau, P.M.3
  • 9
    • 0026175786 scopus 로고
    • An analytic net weighting approach for performance optimization in circuit placement
    • R. S. Tsay and J. Koehl, "An analytic net weighting approach for performance optimization in circuit placement," in Proc. ACM/IEEE Design Automation Conference, pp. 620-625, 1991.
    • (1991) Proc. ACM/IEEE Design Automation Conference , pp. 620-625
    • Tsay, R.S.1    Koehl, J.2
  • 11
    • 0032659075 scopus 로고    scopus 로고
    • Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
    • A. Marquardt, V. Betz, and J. Rose, "Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density," in ACM Symposium on FPGAs, pp. 37-46, 1999.
    • (1999) ACM Symposium on FPGAs , pp. 37-46
    • Marquardt, A.1    Betz, V.2    Rose, J.3
  • 13
    • 0037919131 scopus 로고    scopus 로고
    • The FPGA place-and-route challenge
    • http://www.eecg.toronto.edu/~vaughn/challenge/challenge.html, "The FPGA place-and-route challenge."


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.