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Volumn , Issue , 2005, Pages 795-800

Power-aware placement

Author keywords

Clock Tree; Dynamic Power; Net Switching Power

Indexed keywords

ELECTRIC CLOCKS; ROUTERS; SWITCHING SYSTEMS;

EID: 27944481842     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065579.1065791     Document Type: Conference Paper
Times cited : (100)

References (21)
  • 11
    • 0026175375 scopus 로고
    • High-perfomance clock routing based on recursive geometric matching
    • A. Kahng, J. Cong, and G. Robins, "High-Perfomance Clock Routing Based on Recursive Geometric Matching," Proc. ACM/IEEE Design Automation Conf., 1991, pp. 322-327.
    • (1991) Proc. ACM/IEEE Design Automation Conf. , pp. 322-327
    • Kahng, A.1    Cong, J.2    Robins, G.3
  • 12
    • 32544438322 scopus 로고    scopus 로고
    • Minimize IC power without sacrificing performance
    • July 15
    • A. Krishnamoorthy, "Minimize IC Power without Sacrificing Performance," EEdesign, July 15, 2004. Available at http://www.eedesign. com/article/showArticle.jhtml?articleId-23901143.
    • (2004) EEdesign
    • Krishnamoorthy, A.1
  • 17
    • 24944566140 scopus 로고    scopus 로고
    • Performance and low power driven VLSI standard cell placement using tabu search
    • S. M. Sait, M. R. Minhas and J. A. Khan, "Performance and Low Power Driven VLSI Standard Cell Placement Using Tabu Search." Proc. Congress on Evolutionary Computation, 2002, pp. 372-377.
    • (2002) Proc. Congress on Evolutionary Computation , pp. 372-377
    • Sait, S.M.1    Minhas, M.R.2    Khan, J.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.