-
2
-
-
0030172836
-
Automatic synthesis of gated clocks for power reduction in sequential circuits
-
L. Benini, P. Siefel, and G. D. Micheli, "Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 15(6) (1996), pp. 630-643.
-
(1996)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, vol.15
, Issue.6
, pp. 630-643
-
-
Benini, L.1
Siefel, P.2
Micheli, G.D.3
-
4
-
-
0026946698
-
Zero skew clock routing with minimum wirelength
-
T. Chao, Y. Hsu, J. Ho, K. Boese, and A. Kahng, "Zero Skew Clock Routing with Minimum Wirelength," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 39(11) (1992), pp. 799-814.
-
(1992)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, vol.39
, Issue.11
, pp. 799-814
-
-
Chao, T.1
Hsu, Y.2
Ho, J.3
Boese, K.4
Kahng, A.5
-
5
-
-
0029701437
-
Simultaneous buffer and wire sizing for performance and power optimization
-
J. Cong, C. K. Koh, arid K. S. Leung, "Simultaneous Buffer and Wire Sizing for Performance and Power Optimization," ACM/IEEE Int. Symp. Low-Power Electronics and Design, 1996, pp. 271-276.
-
(1996)
ACM/IEEE Int. Symp. Low-power Electronics and Design
, pp. 271-276
-
-
Cong, J.1
Koh, C.K.2
Leung, A.K.S.3
-
6
-
-
2942635242
-
Power-aware clock tree planning
-
M. Donno, E. Macci, and L. Mazzoni, "Power-Aware Clock Tree Planning," Proc. ACM/IEEE Int. Symp. Physical Design, 2004, pp. 138-147.
-
(2004)
Proc. ACM/IEEE Int. Symp. Physical Design
, pp. 138-147
-
-
Donno, M.1
Macci, E.2
Mazzoni, L.3
-
7
-
-
0035369246
-
Activity-driven clock design
-
A. Farrahi, C. Chen, A. Srivastava, G. Tellez, and M. Sarrafzadeh, "Activity-Driven Clock Design," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 20(6) (2001), pp. 705-714.
-
(2001)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, vol.20
, Issue.6
, pp. 705-714
-
-
Farrahi, A.1
Chen, C.2
Srivastava, A.3
Tellez, G.4
Sarrafzadeh, M.5
-
8
-
-
0032071753
-
High-performance microproccesor design
-
P. E. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R. L. Allmon, "High-Performance Microproccesor Design," IEEE Journal of Solid-State Circuits, 33(5) (1998), pp. 676-686.
-
(1998)
IEEE Journal of Solid-state Circuits
, vol.33
, Issue.5
, pp. 676-686
-
-
Gronowski, P.E.1
Bowhill, W.J.2
Preston, R.P.3
Gowan, M.K.4
Allmon, R.L.5
-
10
-
-
0025546578
-
Clock routing for high-perfomance ICs
-
M. Jackson, A. Srinivason, and E. Kuh, "Clock Routing for High-Perfomance ICs," Proc. ACM/IEEE Design Automation Conf., 1990, pp. 573-579.
-
(1990)
Proc. ACM/IEEE Design Automation Conf.
, pp. 573-579
-
-
Jackson, M.1
Srinivason, A.2
Kuh, E.3
-
11
-
-
0026175375
-
High-perfomance clock routing based on recursive geometric matching
-
A. Kahng, J. Cong, and G. Robins, "High-Perfomance Clock Routing Based on Recursive Geometric Matching," Proc. ACM/IEEE Design Automation Conf., 1991, pp. 322-327.
-
(1991)
Proc. ACM/IEEE Design Automation Conf.
, pp. 322-327
-
-
Kahng, A.1
Cong, J.2
Robins, G.3
-
12
-
-
32544438322
-
Minimize IC power without sacrificing performance
-
July 15
-
A. Krishnamoorthy, "Minimize IC Power without Sacrificing Performance," EEdesign, July 15, 2004. Available at http://www.eedesign. com/article/showArticle.jhtml?articleId-23901143.
-
(2004)
EEdesign
-
-
Krishnamoorthy, A.1
-
13
-
-
16244422171
-
Interconnect-power dissipation in a microprocessor
-
N. Magen, A. Kolodny, U. Weiser, and N. Shamir, "Interconnect-power Dissipation in a Microprocessor," Proc. Workshop on System Level Interconnect Prediction, 2004, pp. 7-13.
-
(2004)
Proc. Workshop on System Level Interconnect Prediction
, pp. 7-13
-
-
Magen, N.1
Kolodny, A.2
Weiser, U.3
Shamir, N.4
-
18
-
-
0031639693
-
Reducing power in high-performance microprocessors
-
V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez, "Reducing Power in High-Performance Microprocessors," Proc. ACM/IEEE Design Automation Conf., 1998, pp. 732-737.
-
(1998)
Proc. ACM/IEEE Design Automation Conf.
, pp. 732-737
-
-
Tiwari, V.1
Singh, D.2
Rajgopal, S.3
Mehta, G.4
Patel, R.5
Baez, F.6
-
19
-
-
0032218438
-
A simultaneous placement and global routing algorithm for FPGAs with power optimization
-
N. Togawa, K. Ukai, M. Yanagisawa and T. Ohtsuki, "A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization," Proc. IEEE Asia-Pacific Conf. Circuits and Systems, 1998, pp. 125-128.
-
(1998)
Proc. IEEE Asia-pacific Conf. Circuits and Systems
, pp. 125-128
-
-
Togawa, N.1
Ukai, K.2
Yanagisawa, M.3
Ohtsuki, T.4
|