Clock-tree aware placement based on dynamic clock-tree building

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2040-2043

  Wang, Yanfeng ^a   Zhou, Qiang ^a   Hong, Xianlong ^a   Cai, Yici ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; OPTIMIZATION;

CLOCK ROUTING; CLOCK TREE BUILDING TECHNIQUE; FORCE DIRECTED PLACEMENT; MULTI LEVEL BOUNDING BOX;

TREES (MATHEMATICS);

EID: 34548845359     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378498     Document Type: Conference Paper

References (9)

1. D. E. Duate, N. Vijaykrishnan and M. J. Irwin, "A clock power model to evaluate impact of architectural and technology optimization," in IEEE TVLSI, 10(6): 844-855, Dec. 2002.
2. Natesan Venkateswaran, Dinesh Bhatia, "Clock-skew constrained cell placement", International Conference on VLSI Design, pp. 146-149, 1996.
3. Natesan Venkateswaran, Dinesh Bhatia, "Clock-skew constrained placement for row based designs", ICCD, pp. 219-220, 1998.
4. Yongqiang Lu, C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu, "Navigating Registers in Placement for Clock Network Minimization", Proceedings of Design Automation Conference, pp. 176-181, 2005.
5. K. P. Vorwerk, A. Kennings, and A. Vannelli, "Engineering details of a stable force-directed placer," in Proc. Int. Conf. on Computer Aided Design, pp. 573-580, November 2004.
6. Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahngt, Sherief Reda, Qinke Wang, "Power-Aware Placement", Proceedings of Design Automation Conference, pp. 795-800, 2005.
7. C.-W. A. Tsao and C.-K. Koh, "UST/DME: a clock tree router for general skew constraints," in Proc. IEEE/ACM ICCAD, pp. 400-405, 2000.
8. W. Liao and L. He, "Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion", in Proc. IEEE/ACM International Conference on Computer-AidedDesign, pp. 574-580, 2003.
9. A. Saurabh and I. Markov, "ISPD02 mixed-size placement benchmarks." http://vlsicad.eecs.uinich.edu/BK/ISPD02bench, Current July 2004.