INTEGRA: Fast multibit flip-flop clustering for clock power saving

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 2, 2012, Pages 192-204

  Jiang, Iris Hui Ru ^a   Chang, Chih Long ^a   Yang, Yu Ming ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Clock power; coordinate transformation; interval graph; multibit flip flops; postplacement optimization

Indexed keywords

CLOCK NETWORK; CLOCK SIGNAL; CLUSTERING SCHEME; CO-ORDINATE TRANSFORMATION; CONCISE REPRESENTATIONS; DENSITY CONSTRAINTS; DYNAMIC POWER; INDUSTRIAL CIRCUITS; INTEGRATED CIRCUIT DESIGNS; INTERVAL GRAPH; MANHATTAN DISTANCE; MULTI-BITS; PARTIAL SEQUENCES; POWER SAVINGS; PROBLEM INSTANCES; SINGLE-BIT; SKEW CONTROL;

ELECTRIC CLOCKS; INTEGRATED CIRCUIT MANUFACTURE; LINEAR TRANSFORMATIONS; POWER SUPPLY CIRCUITS;

FLIP FLOP CIRCUITS;

EID: 84863033814     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2177459     Document Type: Conference Paper

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