ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 747-755

  Kim, Myung Chul ^a   Markov, Igor L ^a  

^a The Department of Civil and Environmental Engineering   (United States)

Author keywords

dynamic river network simulation; Saint Venant equations; SPICE

Indexed keywords

INTERCONNECT MODELS; LAGRANGE OPTIMIZATION; NONCONVEX PROBLEM; PRIMAL-DUAL; RIVER NETWORK; RUNTIMES; SAINT VENANT EQUATION; SUB-PROBLEMS;

BENCHMARKING; COMPUTER SIMULATION; SPICE;

COMPUTER AIDED DESIGN;

EID: 84863548619     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228496     Document Type: Conference Paper

References (35)

1. S. N. Adya, I. L. Markov, P. G. Villarrubia, "On Whitespace and Stability in Physical Synthesis,"Integration, the VLSI Journal vol. 39/4, 2006, pp. 340-362.
2. S. N. Adya, I. L. Markov, "Combinatorial techniques for Mixed-size Placement," ACM Trans. Design Autom. Electr. Syst. 10(1), 2005, pp. 58-90.
3. R. K. Ahuja, T. L. Magnati, J. B. Orlin, "Network Flows: Theory, Algorithms, and Applications," Prentice Hall 1993.
4. C. J. Alpert, T. F. Chan, A. B. Kahng, I. L. Markov, P. Mulet, "Faster Minimization of Linear Wirelength for Global Placement," IEEE Trans. on CAD of Integrated Circuits and Systems 17(1), 1998, pp. 3-13. (Pubitemid 128744863)
5. C. J. Alpert et al., "Techniques for Fast Physical Synthesis," Proc. IEEE 95(3), 2007, pp. 573-599.
6. D. P. Bertsekas, "Nonlinear Programming," 2nd ed., Athena Scientific 1999.
7. S. Boyd, L. Xiao, A. Mutapcic, "Subgradient Methods,"Notes for EE392o, Stanford University 2003. http://www.stanford.edu/class/ee392o/subgrad- method.pdf
8. T. F. Chan, J. Cong, E. Radke, "A Rigorous Framework for Convergent Net-weighting Schemes in Timing-driven Placement," ICCAD 2009, pp. 288-294.
9. T. F. Chan, J. Cong, J. Shinnerl, K. Sze, M. Xie, "mPL6: Enhanced Multilevel Mixed-Size Placement," ISPD 2006, pp. 212-214.
10. H.-C. Chen et al., "Constraint Graph-based Macro Placement for Modern Mixed-size Circuit Designs," ICCAD 2008, pp. 218-223.
11. T.-C. Chen et al.,"MP-trees: A Packing-based Macro Placement Algorithm for Mixed-size Designs,"IEEE TCAD 27(9) 2008, pp. 1621-1634.
12. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, Y.-W. Chang, "NTUPlace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints," IEEE TCAD 27(7) 2008, pp.1228-1240.
13. Y.-L. Chuang et al., "Design-hierarchy Aware Mixed-size Placement for Routability Optimization," ICCAD 2010, pp. 663-668.
14. J. Cong, M. Romesis, J. Shinnerl, "Robust Mixed-Size Placement Under Tight White-Space Constraints," ICCAD 2005, pp. 165-172.
15. P. E. Gill, D. P. Robinson, "A Primal-Dual Augmented Lagrangian," Computational Optimization and Applications 2010, DOI: 10.1007/s10589-010-9339-1.
16. K. C. Kiwiel, T. Larsson, P. O. Lindberg,"Lagrangian Relaxation via Ballstep Subgradient Methods,"Mathematics of Operations Research 32(3), 2007, pp. 669-686. http://mor.journal.informs.org/content/32/3/669 (Pubitemid 351159476)
17. C. Li, C.-K. Koh, "Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement,"ISQED 2007, pp. 829-834.
18. X. He, T. Huang, L. Xiao, H. Tian, G. Cui, E. F. Y Young, "Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement," ICCAD 2011, pp. 74-79.
19. M.-K. Hsu, Y.-W. Chang, V. Balabanov, "TSV-aware Analytical Placement for 3D IC Designs," DAC'11, pp. 664-669.
20. A. B. Kahng, Q. Wang, "A Faster Implementation of APlace," ISPD 2006, pp. 218-220.
21. A. A. Kennings, I. L. Markov, "Smoothening Max-terms and Analytical Minimization of Half-Perimeter Wirelength," VLSI Design 2002, 14(3), pp. 229-237.
22. A. B. Kahng, J. Lienig, I. L. Markov, J. Hu, "VLSI Physical Design: from Graph Partitioning to Timing Closure," Springer 2011, 312 pages.
23. M.-C. Kim, D.-J. Lee, I. L. Markov, "SimPL: An Effective Placement Algorithm," IEEE TCAD 31(1), 2012, pp. 50-60.
24. M.-C. Kim, J. Hu, D.-J. Lee, I. L. Markov, "A SimPLR method for Routability-driven Placement" ICCAD 2011.
25. D.-J. Lee, I. L. Markov, "Obstacle-Aware Clock-tree Shaping During Placement," ISPD 2011, pp. 123-130.
26. G.-J. Nam, J. Cong, "Modern Circuit Placement: Best Practices and Results," Springer 2007.
27. A. N. Ng et al., "Solving Hard Instances of Floorplacement," ISPD 2006, pp. 78-85.
28. M. Pan, N. Viswanathan, C. Chu, "An Efficient & Effective Detailed Placement Algorithm," ICCAD 2005, pp. 48-55.
29. A. E. Ruehli, P. K. Wolff, and G. Goertzel, "Analytical Power/Timing Optimization Technique for Digital Systems," DAC 1977, pp. 142-146.
30. G.Sigl, K.Doll, F.Johannes,"Analytical Placement:A Linear or a Quadratic Objective Function?" DAC'91, pp. 427-432.
31. P. Spindler, U. Schlichtmann, F. M. Johannes, "Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model," IEEE TCAD 27(8) 2008, pp. 1398-1411.
32. N. Viswanathan, M. Pan, C. Chu, "FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control," ASPDAC 2007, pp. 135-140.
33. N. Viswanathan et al., "RQL: Global Placement via Relaxed Quadratic Spreading and Linearization," DAC 2007, pp. 453-458.
34. S. I. Ward et al., "Quantifying Academic Placer Performance on Custom Designs, " ISPD 2011, pp. 91-98.
35. J. Z. Yan et al., "Handling Complexities in Modern Large-scale Mixed-size Circuit Designs," DAC 2009.