Techniques for fast physical synthesis

Proceedings of the IEEE

Volumn 95, Issue 3, 2007, Pages 573-599

  Alpert, Charles J ^a   Karandikar, Shrirang K ^a   Li, Zhuo ^a   Nam, Gi Joon ^a   Quay, Stephen T ^b   Ren, Haoxing ^b   Sze, C N ^a   Villarrubia, Paul G ^b   Yildiz, Mehmet C ^b  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBM   (United States)

Author keywords

Circuit optimization; Circuit synthesis; CMOS integrated circuits; Design automation

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN;

CIRCUIT OPTIMIZATION; CIRCUIT SYNTHESIS; DESIGN AUTOMATIONS; DESIGN PRODUCTIVITY; LOGIC STRUCTURES; PHYSICAL SYNTHESIS; SIGNAL INTEGRITY; TIMING SPECIFICATIONS;

ITERATIVE METHODS;

EID: 43349096114     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2006.890096     Document Type: Article

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