RUMBLE: An incremental timing-driven physical-synthesis optimization algorithm

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 12, 2008, Pages 2156-2168

  Papa, David A ^a,b   Luo, Tao ^c,d   Moffitt, Michael D ^b   Sze, C N ^b   Li, Zhuo ^b   Nam, Gi Joon ^b   Alpert, Charles J ^b   Markov, Igor L ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c The University of Texas at Austin   (United States)

^d MAGMA DESIGN AUTOMATION   (United States)

Author keywords

Static timing analysis; Timing driven placement

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUITS; OPTIMIZATION; SYSTEMS ANALYSIS;

ASIC DESIGNS; CRITICAL PATHS; CYCLE TIMES; GATE SIZINGS; MULTIPLE GATES; OPTIMIZATION ALGORITHMS; STATIC TIMING ANALYSES; STATIC TIMING ANALYSIS; SYNTHESIS TOOLS; TIMING MODELS; TIMING-DRIVEN PLACEMENT;

TIME MEASUREMENT;

EID: 56749100421     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2006155     Document Type: Conference Paper

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