BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 9, 2008, Pages 1607-1620

  Brenner, Ulrich ^a   Struzyna, Markus ^a   Vygen, Jens ^a  

^a UNIVERSITY OF BONN   (Germany)

Author keywords

Layout; Network flows; Physical design; Placement; Quadratic optimization

Indexed keywords

CHLORINE COMPOUNDS; CONTRACTS; COST ACCOUNTING; ELECTRIC BATTERIES; MATHEMATICAL PROGRAMMING; SYSTEMS ENGINEERING;

LAYOUT; NETWORK FLOWS; PHYSICAL DESIGN; PLACEMENT; QUADRATIC OPTIMIZATION;

COMBINATORIAL MATHEMATICS;

EID: 50549085604     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.927674     Document Type: Article

References (48)

1. S. N. Adya and I. L. Markov, "Consistent placement of macro-blocks using floorplanning and standard-cell placement," in Proc. IEEE/ACM Int. Symp. Phys. Des., 2002, pp. 12-17.
2. C. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov, and K. Yan, "Quadratic placement revisited," in Proc. 34th IEEE/ACM Des. Autom. Conf., 1997, pp. 752-757.
3. C. J. Alpert, T. F. Chan, A. B. Kahng, I. L. Markov, and P. Mulet, "Faster minimization of linear wirelength for global placement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 17, no. 1, pp. 3-13, Jan. 1998.
4. U. Brenner, "A faster polynomial algorithm for the unbalanced Hitchcock transportation problem," Oper. Res. Lett., vol. 36, no. 4, pp. 408-413, 2008.
5. U. Brenner, A. Pauli, and J. Vygen, "Almost optimum placement legalization by minimum cost flow and dynamic programming," in. Proc. IEEE/ACM Int. Symp. Phys. Des., 2004, pp. 2-9.
6. U. Brenner and A. Rohe, "An effective congestion driven placement framework," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 4, pp. 387-394, Apr. 2003.
7. U. Brenner and M. Struzyna, "Faster and better global placement by a new transportation problem," in Proc. 42nd IEEE/ACM Des. Autom. Conf., 2005, pp. 591-596.
8. U. Brenner and J. Vygen, "Faster optimal single-row placement with fixed ordering," in IEEE Proc. Des. Autom. Test Eur., 2000, pp. 117-121.
9. U. Brenner and J. Vygen, "Worst-case ratios of networks in the rectilinear plane," Networks, vol. 38, no. 3, pp. 126-139, 2001.
10. U. Brenner and J. Vygen, "Legalizing a placement with minimum total movement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 12, pp. 1597-1613, Dec. 2004.
11. U. Brenner and J. Vygen, "Analytical methods in VLSI placement," in Handbook of Algorithms for VLSI Physical Design Automation, C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, Eds. New York: Taylor & Francis, to be published.
12. T. Chan, J. Cong, M. Romesis, J. Shinnerl, K. Sze, and M. Xie, "mpl6: A robust multilevel mixed-size placement engine," in Proc. IEEE/ACM Int. Symp. Phys. Des., 2005, pp. 227-229.
13. T. F. Chan, J. Cong, and K. Sze, "Multilevel generalized force-directed method for circuit placement," in Proc. IEEE/ACM Int. Symp. Phys. Des., 2005, pp. 185-192.
14. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "A high-quality mixed-size analytical placer considering preplaced blocks and density constraints," in Proc. IEEE Int. Conf. Comput.-Aided Des., 2006, pp. 187-192.
15. H. Eisenmann and F. M. Johannes, "Generic global placement and floorplanning," in Proc. 35th IEEE/ACM Des. Autom. Conf., 1998, pp. 269-274.
16. U. Fassnacht and J. Schietke, "Timing analysis and optimization of a high-performance CMOS processor chipset," in Proc. IEEE Des. Autom. Test Eur., 1998, pp. 325-331.
17. S. Held, "Fast gate sizing and timing closure for multi-million cell designs," Res. Inst. Discrete Math., Univ. Bonn, Bonn, Germany, Rep. 07969, 2007.
18. S. Held, B. Korte, J. Maßberg, M. Ringe, and J. Vygen, "Clockscheduling and clocktree construction for high performance ASICs," in Proc. IEEE Int. Conf. Comput.-Aided Des., 2003, pp. 232-239.
19. M. R. Hestenes, Conjugate Direction Methods in Optimization. Heidelberg, Germany: Springer-Verlag, 1980.
20. M. R. Hestenes and E. Stiefel, "Methods of conjugate gradients for solving linear systems," J. Res. Nat. Bur. Stand., vol. 49, no. 6, pp. 409-439, Dec. 1952.
21. A. Hetzel, "A sequential detailed router for huge grid graphs," in Proc. IEEE Des. Autom. Test Eur., 1998, pp. 332-338.
22. W. Hou, H. Yu, X. Hong, Y. Cai, W. Wu, J. Gu, and W. H. Kao, "A new congestion-driven placement algorithm, based on cell inflation," in Proc. Asia South Pac. Des. Autom. Conf., 2001, pp. 605-608.
23. D. J.-H. Huang and A. B. Kahng, "Partitioning-based standard-cell global placement with an exact objective," in Proc. IEEE/ACM Int. Symp. Phys. Des., 1997, pp. 18-25.
24. A. B. Kahng, P. Tucker, and A. Zelikovsky, "Optimization of linear placements for wirelength minimization with free sites," in Proc. Asia South Pac. Des. Autom. Conf., 1999, pp. 241-244.
25. A. B. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer," in Proc. IEEE/ACM Int. Symp. Phys. Des., 2004, pp. 18-25.
26. A. Khatkhate, C. Li, A. R. Agnihotri, M. C. Yildiz, S. Ono, C.-K. Koh, and P. H. Madden, "Recursive bisection based mixed block placement," in Proc. IEEE/ACM Int. Symp. Phys. Des., 2004, pp. 84-89.
27. J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization," IEEE Trans. Comput-Aided Design Integr. Circuits Syst., vol. 10, no. 3, pp. 356-365, Mar. 1991.
28. J. Koehl, U. Baur, T. Ludwig, B. Kick, and T. Pflueger, "A flat, timing-driven design system, for a high-performance CMOS processor chipset," in Proc. IEEE Des. Autom. Test Eur., 1998, pp. 312-320.
29. J. Koehl, D. E. Lackey, and G. W. Doerre, "IBM's 50 million gate ASICs," in Proc. IEEE Asia South Pac. Des. Autom. Conf., 2003, pp. 628-634.
30. B. Korte, D. Rautenbach, and J. Vygen, "BonnTools: Mathematical innovation for layout and timing closure of systems on a chip," Proc. IEEE, vol. 95, no. 3, pp. 555-572, Mar. 2007.
31. B. Korte and J. Vygen, Combinatorial Optimization: Theory and Algorithms, 4th ed. Berlin, Germany: Springer-Verlag, 2008.
32. D. Müller, "Optimizing yield in global routing," in Proc. IEEE Int. Conf. Comput-Aided Des., 2006, pp. 480-486.
33. G.-J. Nam, "ISPD 2006 Placement contest: Benchmark suite and results," in Proc. IEEE/ACM Int. Symp. Phys. Des., 2006, p. 167.
34. G.-J. Nam, S. Reda, C. J. Alpert, P. G. Villarubia, and A. B. Kahng, "A fast hierarchical quadratic placement algorithm," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 4, pp. 678-691, Apr. 2006.
35. P. J. Ossler, "Placement driven synthesis case studies on two sets of two chips: Hierarchical and flat," in Proc. IEEE/ACM Int. Symp. Phys. Des., 2004, pp. 190-197.
36. J. A. Roy, S. N. Adya, D. A. Papa, and I. L. Markov, "Min-cut floorplacement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 7, pp. 1313-1326, Jul. 2006.
37. G. Sigl, K. Doll, and F. M. Johannes, "Analytical placement: A linear or quadratic objective function?" in Proc. 28th IEEE/ACM Des. Autom. Conf., 1991, pp. 427-432.
38. P. Spindler and F. Johannes, "Fast and robust quadratic placement combined with, an exact linear net model," in Proc. Int. Conf. Comput.-Aided Des., 2006, pp. 179-186.
39. J. Stoer and R. Burlisch, Introduction to Numerical Analysis, 3rd ed. New York: Springer-Verlag, 2002.
40. M. Struzyna, "VLSI placement with position constraints and local densities," Res. Inst. Discrete Math., Univ. Bonn, Bonn, Germany, Tech. Rep. No. 07967, 2007.
41. T. Taghavi, X. Yang, B.-K. Choi, M. Wang, and M. Sarrafzadeh, "Dragon 2005: Large scale mixed-sized placement tool," in Proc. IEEE/ACM Int. Symp. Phys. Des., 2005, pp. 42-47.
42. N. Viswanathan, M. Pan, and C. Chu, "FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control," in Proc. Asia South Pac. Des. Autom. Conf., 2007, pp. 135-140.
43. J. Vygen, "Algorithms for large-scale flat placement," in Proc. 34th IEEE/ACM Des. Autom. Conf., 1997, pp. 746-751.
44. J. Vygen, "Algorithms for detailed placement of standard cells," in Proc. IEEE Des. Autom. Test Eur., 1998, pp. 321-324.
45. J. Vygen, "Geometric quadrisection in linear time, with application to VLSI placement," Discrete Optim., vol. 2, no. 4, pp. 362-390, Dec. 2005.
46. J. Vygen, "New theoretical results on quadratic placement," Integr. VLSI J., vol. 40, no. 3, pp. 305-314, Apr. 2007.
47. Z. Xiu, J. D. Ma, S. M. Fowler, and R. A. Rutenbar, "Large-scale placement by grid-warping," in Proc. 41st IEEE/ACM Des. Autom. Conf., 2004, pp. 351-356.
48. Z. Xiu and R. A. Rutenbar, "Timing-driven placement by grid-warping," in Proc. 42nd. IEEE/ACM Des. Autom. Conf., 2005, pp. 585-590.