Assembling 2-D blocks into 3-D chips

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 2, 2012, Pages 228-241

  Knechtel, Johann ^a   Markov, Igor L ^b   Lienig, Jens ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

3 D IC design styles; 3 D integrated circuits (ICs); floorplan optimization; intellectual property (IP) blocks; through silicon via (TSV) planning; TSV islands

Indexed keywords

3-D INTEGRATED CIRCUIT; FLOORPLANS; IC DESIGNS; INTELLECTUAL PROPERTY (IP) BLOCKS; TSV ISLANDS;

INTEGRATED CIRCUITS; INTEGRATION; INTELLECTUAL PROPERTY; MEMS; MICROELECTROMECHANICAL DEVICES;

THREE DIMENSIONAL;

EID: 84856433796     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2174640     Document Type: Conference Paper

References (47)

1. S. Borkar, "3D integration for energy efficient system design," in Proc. Des. Automat. Conf., 2011, pp. 214-219.
2. ITRS. (2009). International Technology Roadmap for Semiconductors [Online]. Available: http://www.itrs.net/Links/2009ITRS/Home2009. htm
3. Global Industry Analysts, Inc. (2010). 3D Chips (3D IC): A Global Market Report [Online]. Available: http://www.prweb.com/releases/3D chips/3D IC/prweb4400904.htm
4. L. Cheng, L. Deng, and M. D. F. Wong, "Floorplanning for 3-D VLSI design," in Proc. Asia South Pacific Des. Automat. Conf., 2005, pp. 405-411.
5. J. Cong, J. Wei, and Y. Zhang, "A thermal-driven floorplanning algorithm for 3D ICs," in Proc. Int. Conf. Comput.-Aided Des., 2004, pp. 306-313. (Pubitemid 40449251)
6. J. Cong and Y. Ma, "Thermal-aware 3D floorplan," in Integrated Circuits and Systems. New York: Springer, 2010, ch. 4, pp. 63-102.
7. P. Zhou, Y. Ma, Z. Li, R. P. Dick, L. Shang, H. Zhou, X. Hong, and Q. Zhou, "3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2007, pp. 590-597.
8. Z. Li, X. Hong, Q. Zhao, S. Zeng, J. Bian, H. Yang, and C. K. Cheng, "Integrating dynamic thermal via planning with 3D floorplanning algorithm," in Proc. Int. Symp. Phys. Des., 2006, pp. 178-185. (Pubitemid 44059914)
9. X. Li, Y. Ma, and X. Hong, "A novel thermal optimization flow using incremental floorplanning for 3D ICs," in Proc. Asia South Pacific Des. Automat. Conf., 2009, pp. 347-352.
10. P. Jain, P. Zhou, C. H. Kim, and S. S. Sapatnekar, "Thermal and power delivery challenges in 3D ICs," in Integrated Circuits and Systems. New York: Springer, 2010, ch. 3, pp. 33-61.
11. E. Wong and S. K. Lim, "Whitespace redistribution for thermal via insertion in 3D stacked ICs," in Proc. Int. Conf. Comput.-Aided Des., 2007, pp. 267-272.
12. M. Pathak, Y.-J. Lee, T. Moon, and S. K. Lim, "Through-silicon-via management during 3D physical design: When to add and how many?" in Proc. Int. Conf. Comput.-Aided Des., 2010, pp. 387-394.
13. A.-C. Hsieh, T.-T. Hwang, M.-T. Chang, M.-H. Tsai, C.-M. Tseng, and H.-C. Li, "TSV redundancy: Architecture and design issues in 3D IC," in Proc. Des. Automat. Test Eur., 2010, pp. 166-171.
14. M.-C. Tsai, T.-C. Wang, and T. T. Hwang, "Through-silicon via planning in 3-D floorplanning," IEEE Trans. Very Large Scale Integr. Syst., vol. 19, no. 8, pp. 1448-1457, Aug. 2011.
15. Y.-J. Lee, M. Healy, and S. K. Lim, "Co-design of reliable signal and power interconnects in 3D stacked ICs," in Proc. Int. Interconn. Technol. Conf., 2009, pp. 56-58.
16. D. H. Kim, K. Athikulwongse, and S. K. Lim, "A study of throughsilicon-via impact on the 3D stacked IC layout," in Proc. Int. Conf. Comput.-Aided Des., 2009, pp. 674-680.
17. Y.-J. Lee, R. Goel, and S. K. Lim, "Multi-functional interconnect cooptimization for fast and reliable 3D stacked ICs," in Proc. Int. Conf. Comput.-Aided Des., 2009, pp. 645-651.
18. A. K. Coskun, A. B. Kahng, and T. S. Rosing, "Temperature-and costaware design of 3D multiprocessor architectures," in Proc. Euromicro Conf. Digit. Syst. Des., 2009, pp. 183-190.
19. M. Jung, J. Mitra, D. Z. Pan, and S. K. Lim, "TSV stress-aware fullchip mechanical reliability analysis andoptimization for 3D IC," in Proc. Des. Automat. Conf., Jun. 2011, pp. 188-193.
20. I. Loi, S. Mitra, T. H. Lee, S. Fujita, and L. Benini, "A low-overhead fault tolerance scheme for TSV-based 3D network on chip links," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2008, pp. 598-602.
21. J.-S. Yang, K. Athikulwongse, Y.-J. Lee, S. K. Lim, and D. Z. Pan, "TSV stress aware timing analysis with applications to 3D-IC layout optimization," in Proc. Des. Automat. Conf., Jun. 2010, pp. 803-806.
22. S. Garg and D. Marculescu, "3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs," in Proc. Int. Symp. Qual. Elec. Des., 2009, pp. 147-155.
23. C. Liu, T. Song, and S. K. Lim, "Signal integrity analysis and optimization for 3D ICs," in Proc. Int. Symp. Qual. Elec. Des., 2011, pp. 42-49.
24. D. H. Kim, S. Mukhopadhyay, and S. K. Lim, "Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs," in Proc. Int. Workshop Syst.-Level Interconn. Pred., 2009, pp. 85-92.
25. Z. Li, X. Hong, Q. Zhou, J. Bian, H. H. Yang, and V. Pitchumani, "Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration," ACM Trans. Des. Automat. Elec. Syst., vol. 11, no. 2, pp. 325-345, Apr. 2006. (Pubitemid 44076232)
26. H.-H. S. Lee and K. Chakrabarty, "Test challenges for 3D integrated circuits," Des. Test Comput., vol. 26, no. 5, pp. 26-35, 2009.
27. D. L. Lewis and H.-H. S. Lee, "Test strategies for 3D die stacked integrated circuits," in Proc. Workshop 3D Integr. Technol. Architecture Des. Autom. Test in Conjunction with Des. Autom. Test Eur., Nice, France, Apr. 2009.
28. R. Fischbach, J. Lienig, and T. Meister, "From 3D circuit technologies and data structures to interconnect prediction," in Proc. Int. Workshop Syst.-Level Interconn. Pred., 2009, pp. 77-84.
29. V. S. Nandakumar and M. Marek-Sadowska, "Layout effects in finegrain 3-D integrated regular microprocessorblocks," in Proc. Des. Automat. Conf., 2011, pp. 639-644.
30. D. Sylvester and K. Keutzer, "A global wiring paradigm for deep submicron design," IEEE Trans. Comput.-Aided Des. Integr. Circuits Sys., vol. 19, no. 2, pp. 242-252, Feb. 2000.
31. Cadence Design Systems, Inc. (2010). 3D ICs with TSVs: Design Challenges and Requirements [Online]. Available: http://www.cadence.com/rl/Resources/white papers/3DIC wp.pdf
32. L. K. Scheffer, "CAD implications of new interconnect technologies," in Proc. Des. Automat. Conf., 2007, pp. 576-581. (Pubitemid 47130031)
33. L. Jiang, Q. Xu, K. Chakrabarty, and T. M. Mak, "Layout-driven testarchitecture design and optimization for 3D SoCs under pre-bond testpin-count constraint," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2009, pp. 191-196.
34. G. H. Loh, Y. Xie, and B. Black, "Processor design in 3D diestacking technologies," IEEE Micro, vol. 27, no. 3, pp. 31-48, May-Jun. 2007.
35. C. Ferri, S. Reda, and R. I. Bahar, "Strategies for improving the parametric yield and profits of 3D ICs," in Proc. Int. Conf. Comput.-Aided Des., 2007, pp. 220-226.
36. M. B. Healy, K. Athikulwongse, R. Goel, M. M. Hossain, D. H. Kim, Y.-J. Lee, D. L. Lewis, T.-W. Lin, C. Liu, M. Jung, B. Ouellette, M. Pathak, H. Sane, G. Shen, D. H. Woo, X. Zhao, G. H. Loh, H. S. Lee, and S. K. Lim, "Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory," in Proc. Custom Integr. Circuits Conf., Sep. 2010, pp. 1-4.
37. K. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, "Thermomechanical reliability of 3-D ICs containing through silicon vias," in Proc. Electron. Compon. Technol. Conf., May 2009, pp. 630-634.
38. X. Zhao, J. Minz, and S. K. Lim, "Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 2, pp. 247-259, Feb. 2011.
39. H. Imai and T. Asano, "Finding the connected components and a maximum clique of an intersection graph of rectangles in the plane," J. Algorith., vol. 4, no. 4, pp. 310-323, 1983.
40. C. H. Papadimitriou and K. Steiglitz, Combinatorial Optimization: Algorithms and Complexity. New York: Dover, 1998.
41. R. Fowler, "Optimal packing and covering in the plane are NP-complete," Inform. Process. Lett., vol. 12, no. 3, pp. 133-137, 1981. (Pubitemid 12458892)
42. S. N. Adya and I. L. Markov, "Consistent placement of macro-blocks using floorplanning and standard-cell placement," in Proc. Int. Symp. Phys. Des., 2002, pp. 12-17. (Pubitemid 35040015)
43. A. B. Kahng, J. Lienig, I. L. Markov, and J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure. New York: Springer, 2011.
44. S. S. Sapatnekar, Timing. Norwell, MA: Kluwer, 2004.
45. M. D. Moffitt, J. A. Roy, I. L. Markov, and M. E. Pollack, "Constraintdriven floorplan repair," ACM Trans. Des. Automat. Electron. Syst., vol. 13, no. 4, pp. 1-13, 2008.
46. D. H. Kim, S. Mukhopadhyay, and S. K. Lim, "TSV-aware interconnect length and power prediction for 3D stacked ICs," in Proc. Int. Interconn. Technol. Conf., 2009, pp. 26-28.
47. R. Topaloglu, "Applications driving 3-D integration and corresponding manufacturingchallenges," in Proc. Des. Automat. Conf., 2011, pp. 214-219.