Placement: Hot or not?

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2012, Pages 283-290

  Alpert, Charles ^a   Li, Zhuo ^a   Nam, Gi Joon ^a   Sze, C N ^a   Viswanathan, Natarajan ^a   Ward, Samuel I ^a  

^a IBM   (United States)

Author keywords

Physical Design; Placement

Indexed keywords

CONSTRAINT MANAGEMENT; DATA PATHS; DESIGN AUTOMATIONS; DESIGN CLOSURE; DESIGN QUALITY; ELECTRONIC DESIGN AUTOMATION; PHYSICAL DESIGN; PLACEMENT; ROUTABILITY; TIME-TO-MARKET;

COMPUTER AIDED DESIGN;

EID: 84872311402     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (56)

1. W.-J. Sun and C. Sechen. Efficient and effective placement for very large circuits. TCAD, 14(3):349-359, 1995.
2. J. Kleinhans, G. Sigl, F. Johannes, and K. Antreich. GORDIAN: VLSI placement by quadratic programming and slicing optimization. TCAD, 10(3):356-365, 1991.
3. R.-S. Tsay, E. S. Kuh, and C.-P. Hsu. PROUD: A sea-of-gates placement algorithm. TDTC, 5(6):44-56, 1988.
4. A. E. Caldwell, A. B. Kahng, and I. L. Markov. Can recursive bisection produce routable placements. In Proc. DAC, pages 477-482, 2000.
5. U. Brenner, M. Struzyna, and J. Vygen. Bonnplace: Placement of leading-edge chips by advanced combinatorial algorithms. TCAD, 27(9):1607-1620, 2008.
6. C. J. Alpert. The ISPD98 circuit benchmark suite. In Proc. ISPD, pages 80-85, 1998.
7. IBM-PLACE Benchmarks. http://er.cs.ucla.edu/benchmarks/ibm-place/.
8. G.-J. Nam, C. J. Alpert, P. Villarrubia, B. Winter, and M. Yildiz. The ISPD2005 placement contest and benchmark suite. In Proc. ISPD, pages 216-220, 2005.
9. N. Viswanathan and C. C.-N. Chu. FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. TCAD, 24(5):722-733, 2005.
10. A. B. Kahng, S. Reda, and Q. Wang. Architecture and details of a high quality, large-scale analytical placer. In Proc. ICCAD, pages 890-897, 2005.
11. T. F. Chan, J. Cong, J. R. Shinnerl, K. Sze, and M. Xie. mPL6: Enhanced multilevel mixed-size placement. In Proc. ISPD, pages 212-214, 2006.
12. P. Spindler and F. M. Johannes. Fast and robust quadratic placement combined with an exact linear net model. In Proc. ICCAD, pages 179-186, 2006.
13. N. Viswanathan, G.-J. Nam, C. J. Alpert, P. Villarubia, H. Ren, and C. Chu. RQL: Global placement via relaxed quadratic spreading and linearization. In Proc. DAC, pages 453-458, 2007.
14. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. TCAD, 27(7):1228-1240, July 2008.
15. M.-C. Kim, D.-J. Lee, and I. L. Markov. SimPL: An effective placement algorithm. TCAD, 31(1):50-60, 2012.
16. N. Viswanathan, C. J. Alpert, C. Sze, Z. Li, G.-J. Nam, and J. A. Roy. The ISPD-2011 Routability-driven placement contest and benchmark suite. In Proc. ISPD, pages 141-146, 2011.
17. N. Viswanathan, C. J. Alpert, C. Sze, Z. Li, and Y. Wei. The DAC 2012 Routability-driven placement contest and benchmark suite. In Proc. DAC, pages 774-782, 2012.
18. N. Viswanathan, C. J. Alpert, C. Sze, Z. Li, and Y. Wei. The ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. In Proc. ICCAD, To Appear, 2012.
19. C.J. Alpert, Z. Li, M.D. Moffitt, G.J. Nam, J.A. Roy, and G. Tellez. What makes a design difficult to route. In Proc. ISPD, pages 7-12, 2010.
20. Z. Li, C.J. Alpert, G.J. Nam, C. Sze, N. Viswanathan, and N.Y. Zhou. Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. In Proc. DAC, pages 465-470, 2012.
21. Y.-J. Chang, Y.-T. Lee, and T.-C. Wang. NTHU-Route 2.0: A fast and stable global router. In Proc. ICCAD, pages 338-343, 2008.
22. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang. Multi-layer global routing considering via and wire capacities. In Proc. ICCAD, pages 350-355, 2008.
23. Y. Xu, Y. Zhang, and C. Chu. FastRoute 4.0: Global router with efficient via minimization. In Proc. ASP-DAC, pages 576-581, 2009.
24. T.-H Wu, A. Davoodi, and J. T. Linderoth. A parallel integer programming approach to global routing. In Proc. DAC, pages 194-199, 2010.
25. J. Hu, J. A. Roy, and I. L. Markov. Completing high-quality routes. In Proc. ISPD, pages 35-41, 2010.
26. W.-H. Liu, W.-C. Kao, Y.-L. Li, and K.-Y. Chao. Multi-threaded collision-aware global routing with bounded-length maze routing. In Proc. DAC, pages 200-205, 2010.
27. J. A. Roy, N. Viswanathan, G.-J. Nam, C. J. Alpert, and I. L. Markov. CRISP: Congestion reduction by iterated spreading during placement. In Proc. ICCAD, pages 357-362, 2009.
28. M.-C. Kim, J. Hu, D.-J. Lee, and I. L. Markov. A SimPLR method for routability-driven placement. In Proc. ICCAD, pages 67-73, 2011.
29. X. He, T. Huang, L. Xiao, H. Tian, G. Cui, and E.F.Y. Young. Ripple: An effective routability-driven placer by iterative cell movement. In Proc. ICCAD, pages 74-79, 2011.
30. M.-K. Hsu, S. Chou, T.H. Lin, and Y.-W. Chang. Routability-driven analytical placement for mixed-size circuit designs. In Proc. ICCAD, pages 80-84, 2011.
31. F.-Y. Chang, S.-H. Chen, R.-S. Tsay, and W.-K. Mak. Cut-demand based routing resource allocation and consolidation for routability enhancement. In Proc. ASP-DAC, pages 533-538, 2011.
32. T. Taghavi et al. New placement prediction and mitigation techniques for local routing congestion. In Proc. ICCAD, pages 621-624, 2010.
33. Y. Zhang and C. Chu. GDRouter: Interleaved global routing and detailed routing for ultimate routability. In Proc. DAC, pages 597-602, 2012.
34. Y. Wei et al. GLARE: Global and local wiring aware routability evaluation. In Proc. DAC, pages 768-773, 2012.
35. R. Shelar. An efficient clustering algorithm for low power clock tree synthesis. In Proc. ISPD, pages 181-188, 2007.
36. R. Puri, L. Stok, and S. Bhattacharya. Keeping hot chips cool. In Proc. DAC, pages 285-288, 2005.
37. Y.-T. Chang, C.-C. Hsu, M.P.-H. Lin, Y.-W. Tsai, and S.-F. Chen. Post-placement power optimization with multi-bit flip-flops. In Proc. ICCAD, pages 218-223, 2010.
38. I.H.-R. Jiang, C.-L. Chang, Y.-M. Yang, E.Y.-W. Tsai, and L.S.-F. Chen. INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs. In Proc. ISPD, pages 115-122, 2011.
39. S. Paik, G.-J. Nam, and Y. Shin. Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. In Proc. ICCAD, pages 640-646, 2011.
40. C.-L. Chang, I.H.-R. Jiang, Y.-M. Yang, E.Y.-W. Tsai, and A.S.-H. Chen. Novel pulsed-latch replacement based on time borrowing and spiral clustering. In Proc. ISPD, pages 121-128, 2012.
41. T. Kong. A novel net weighting algorithm for timing-driven placement. In Proc. ICCAD, pages 172-176, 2002.
42. H. Ren, D. Z. Pan, and D. S. Kung. Sensitivity guided net weighting for placement-driven synthesis. TCAD, 24(5):711-721, May 2005.
43. C.R. Chen B. Halpin and N. Sehgal. Timing driven placement using physical net constraints. In Proc. DAC, pages 780-783, 2001.
44. K. Rajagopal, T. Shaked, Y. Perasuram, T. Cao, A. Chowdhary, and B. Halpin. Timing driven force directed placement with physical net constraints. In Proc. ISPD, pages 60-66, 2003.
45. M. Stabenfeldt C.C. Chang, J. Lee and R.S. Tsay. A practical all-path timing-driven place and route design system. In Proc. IEEE Conference on Asia-Pacific Circuis and Systems, pages 560-563, 1994.
46. T. Luo, D. Newmark, and D. Z. Pan. A new LP based incremental timing driven placement for high performance designs. In Proc. DAC, pages 1115-1120, 2006.
47. M. D. Moffitt, D. A. Papa, Z. Li, and C. J. Alpert. Path smoothing via discrete optimization. In Proc. DAC, pages 8-13, 2008.
48. G.J. Nam, D. Papa, M. Moffitt, and C. Alpert. Toward the integration of incremental physical synthesis optimizations. In Proc. ISVLSI-DAT, pages 23-26, 2009.
49. N. Viswanathan, G.-J. Nam, J. A. Roy, Z. Li, C. J. Alpert, S. Ramji, and C. Chu. ITOP: Integrating timing optimization within placement. In Proc. ISPD, pages 83-90, 2010.
50. R. X. T. Nijssen and J. A. G. Jess. Two-dimensional datapath regularity extraction. In IFIP Workshop on Logic and Architecture Synthesis, pages 110-117, 1996.
51. P. Ienne and A. GrieBing. Practical experiences with standard-cell based datapath design tools. In Proc. DAC, pages 396-401, 1998.
52. S. Ono and P. H. Madden. On structure and suboptimality in placement. In Proc. ASP-DAC, pages 331-336, 2005.
53. S. I. Ward, D. A. Papa, Z. Li, C. N. Sze, C. J. Alpert, and E. Swartzlander. Quantifying academic placer performance on custom designs. In Proc. ISPD, pages 91-98, 2011.
54. S. I. Ward, M.-C. Kim, N. Viswanathan, Z. Li, C. Alpert, E. Swartzlander, and D. Z. Pan. Keep it straight: Teaching placement how to better handle designs with datapaths. In Proc. ISPD, pages 79-86, 2012.
55. S. Chou, M.-K. Hsu, and Y.-W. Chang. Structure-aware placement for datapath-intensive circuit designs. In Proc. DAC, pages 762-767, 2012.
56. S. I. Ward, D. Ding, and D. Z. Pan. PADE: A high-performance mixed-size placer with automatic datapath extraction and evaluation through high-dimensional data learning. In Proc. DAC, pages 768-773, 2012.