Seeing the forest and the trees: Steiner wirelength optimization in placement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 4, 2007, Pages 632-644

  Roy, Jarrod A ^b   Markov, Igor L ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Algorithms; Design automation; Integrated circuit layout; Routing; Very large scale integration

Indexed keywords

DESIGN AUTOMATION; PLACEMENT ALGORITHM; ROUTED WIRELENGTH (RWL);

ALGORITHMS; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; ROUTING ALGORITHMS; VLSI CIRCUITS;

TREES (MATHEMATICS);

EID: 33947609584     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.888260     Document Type: Article

References (31)

1. S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and L. Markov, "Unification of partitioning, placement and floorplanning," in Proc. ICCAD, 2004, pp. 550-557.
2. A. Agnihotri et al., "Fractional cut: Improved recursive bisection placement," in Proc. ICCAD, 2003, pp. 307-310.
3. U. Brenner and A. Rohe, "An effective congestion driven placement framework," in Proc. ISPD, San Diego, CA, 2002, pp. 6-11.
4. A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky, "On wirelength estimations for row-based placement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 9, pp. 1265-1278, Sep. 1999.
5. A. E. Caldwell, A. B. Kahng, and I. L. Markov, "Can recursive bisection alone produce routable placements?" in Proc. DAC, Los Angeles, CA, 2000, pp. 477-182
6. _, "Design and implementation of move-based heuristics for VLSI hypergraph partitioning," ACM J. Exp. Algorithms, vol. 5, 2000.
7. _, "Optimal partitioners and end-case placers for top-down placement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 11, pp. 1304-1314, Nov. 2000.
8. H. H. Chan, S. N. Adya, and I. L. Markov, "Are floorplan representations useful in digital design?" in Proc. ISPD, San Francisco, CA, 2005, pp. 129-136
9. C. C. Chang, J. Cong, M. Romesis, and M. Xie, "Optimality and scalability study of existing placement algorithms," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 4, pp. 537-549, Apr. 2004.
10. T. C. Chen, Y. W. Chang, and S. C. Lin, "IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs," in Proc. ICCAD, 2005, pp. 159-164.
11. C.-L. Cheng, "RISA: Accurate and efficient placement routability modeling," in Proc. ICCAD, 1994, pp. 690-695.
12. C. C. N. Chu and Y.-C. Wong, "Fast and accurate rectilinear Steiner minimal tree algorithm for VLSI design," in Proc. ISPD, 2005, pp. 28-35.
13. A. E. Dunlop and B. W. Kernighan, "A procedure for placement of standard cell VLSI circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. CAD-4, no. 1, pp. 92-98, Jan. 1985.
14. C. M. Fiduccia and R. M. Mattheyses, "A linear time heuristic for improving network partitions," in Proc. DAC, 1982, pp. 175-181.
15. M. R. Garey and D. S. Johnson, "The rectilinear Steiner problem is NP-complete," SIAM J. Appl. Math., vol. 32, no. 4, pp. 826-834, Jun. 1977.
16. D. J.-H. Huang and A. B. Kahng, "Partitioning-based standard-cell global placement with an exact objective," in Proc. ISPD, 1997, pp. 18-25.
17. IWLS 2005 Benchmarks. [Online], Available: http://www.iwls.org/ iwls2005/benchmarks.html
18. D. Jariwala and J. Lillis, "On interactions between routing and detailed placement," in Proc. ICCAD, 2004, pp. 387-393.
19. A. B. Kahng, I. I. Mandoiu, and A. Zelikovsky, "Highly scalable algorithms for rectilinear and octilinear Steiner trees," in Proc. ASPDAC, 2003, pp. 827-833.
20. A. B. Kahng and O. Robins, "A new class of iterative Steiner tree heuristics with good performance," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 11, no. 7, pp. 893-902, Jul. 1992.
21. A. B. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 5, pp. 734-747, May 2005.
22. A. B. Kahng and X. Xu, "Accurate pseudo-constructive wirelength and congestion estimation," in Proc. SLIP, 2003, pp. 81-86.
23. C. Li, M. Xie, C. K. Koh, J. Cong, and P. H. Madden, "Routability- driven placement and white space allocation," in Proc. ICCAD, 2004, pp. 394-401.
24. J. A. Roy, S. N. Adya, D. A. Papa, and I. L. Markov, "Min-cut floorplacement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 7, pp. 1313-1326, Jul. 2006.
25. J. A. Roy, J. F. Lu, and I. L. Markov, "Seeing the forest and the trees: Steiner wirelength optimization in placement," in Proc. ISPD, San Jose, CA, 2006, pp. 78-85.
26. N. Selvakkumaran, P. Parakh, and G. Karypis, "Perimeter-degree: A priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement," in Proc. SLIP, 2003, pp. 53-59.
27. N. Selvakkumaran and G. Karypis, "Theto - A fast, scalable and high-quality partitioning driven placement tool," Univ. Minnesota, Minneapolis, MN, Tech. Rep. 04-040, 2004.
28. P. Suaris and G. Kedem, "Quadrisection: A new approach to standard cell layout," in Proc. ICCAD, 1987, pp. 474-477.
29. K. Takahashi et al., "Min-cut placement with global objective functions for large scale sea-of-gates arrays," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 14, no. 4. pp. 434-446, Apr. 1995.
30. J. Westra, C. Bartels, and P. Groeneveld, "Probabilistic congestion prediction," in Proc. ISPD, 2004, pp. 204-209.
31. X. Yang, B. K. Choi, andM. Sarrafzadeh, "Routability driven white space allocation for fixed-die standard-cell placement," in Proc. ISPD, 2002, pp. 42-49.