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Volumn 10, Issue 1, 2005, Pages 58-90

Combinatorial techniques for mixed-size placement

Author keywords

Floorplanning; Placement; VLSI

Indexed keywords


EID: 29144472522     PISSN: 10844309     EISSN: 10844309     Source Type: Journal    
DOI: 10.1145/1044111.1044116     Document Type: Article
Times cited : (34)

References (41)
  • 3
    • 0036377317 scopus 로고    scopus 로고
    • Consistent placement of macro-blocks using floorplanning and standard-cell placement
    • San Diego, CA
    • ADYA, S. N. AND MARKOV, I. L. 2002. Consistent placement of macro-blocks using floorplanning and standard-cell placement. In Proceedings of the International Symposium on Physical Design (San Diego, CA). 12-17.
    • (2002) Proceedings of the International Symposium on Physical Design , pp. 12-17
    • Adya, S.N.1    Markov, I.L.2
  • 4
    • 0742321357 scopus 로고    scopus 로고
    • Fixed-outline floorplanning: Enabling hierarchical design
    • ADYA, S. N. AND MARKOV, I. L. 2003. Fixed-outline floorplanning: Enabling hierarchical design. IEEE Trans. VLSI Syst. 11, 6 (Dec.), 1120-1135.
    • (2003) IEEE Trans. VLSI Syst. , vol.11 , Issue.6 DEC , pp. 1120-1135
    • Adya, S.N.1    Markov, I.L.2
  • 14
    • 0034313430 scopus 로고    scopus 로고
    • Optimal partitioners and end-case placers for standard-cell layout
    • CALDWELL, A. E., KAHNG, A. B., AND MARKOV, I. L. 2000b. Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. Comput.-Aided Des. 19, 11, 1304-1314.
    • (2000) IEEE Trans. Comput.-Aided Des. , vol.19 , Issue.11 , pp. 1304-1314
    • Caldwell, A.E.1    Kahng, A.B.2    Markov, I.L.3
  • 15
    • 0242636372 scopus 로고    scopus 로고
    • Hierarchical whitespace allocation in top-down placement
    • CALDWELL, A. E., KAHNG, A. B., AND MARKOV, I. L. 2003. Hierarchical whitespace allocation in top-down placement. IEEE Trans. Comput.-Aided Des. 22, 11 (Nov.), 716-724.
    • (2003) IEEE Trans. Comput.-Aided Des. , vol.22 , Issue.11 NOV , pp. 716-724
    • Caldwell, A.E.1    Kahng, A.B.2    Markov, I.L.3
  • 16
    • 84954416950 scopus 로고    scopus 로고
    • Multi-level placement for large-scale mixed-size ic designs
    • KitaKyushu, Japan
    • CHANG, C., CONG, J., AND YUAN, X. 2003. Multi-level placement for large-scale mixed-size ic designs. In Proceedings of the ASPDAC (KitaKyushu, Japan). 325-330.
    • (2003) Proceedings of the ASPDAC , pp. 325-330
    • Chang, C.1    Cong, J.2    Yuan, X.3
  • 17
    • 84872317029 scopus 로고    scopus 로고
    • Hierarchical global floorplacement using simulated annealing and network flow area migration
    • Munich, Germany
    • CHOI, W. AND BAZARGAN, K. 2003. Hierarchical global floorplacement using simulated annealing and network flow area migration. In Proceedings of the DATE (Munich, Germany). 1104-1105.
    • (2003) Proceedings of the DATE , pp. 1104-1105
    • Choi, W.1    Bazargan, K.2
  • 19
    • 0028516550 scopus 로고
    • Iterative placement improvement by network flow methods
    • DOLL, K., JOHANNES, F. M., AND ANTREICH, K. J. 1994. Iterative placement improvement by network flow methods. IEEE Trans. Comput.-Aided Des. 13, 10 (Oct.), 1189-1200.
    • (1994) IEEE Trans. Comput.-Aided Des. , vol.13 , Issue.10 OCT , pp. 1189-1200
    • Doll, K.1    Johannes, F.M.2    Antreich, K.J.3
  • 20
    • 0034474792 scopus 로고    scopus 로고
    • Effective partition-driven placement with simultaneous level processing and a global net view
    • San Jose, CA
    • DUTT, S. 2000. Effective partition-driven placement with simultaneous level processing and a global net view. In Proceedings of the International Conference on Computer Aided Design (San Jose, CA). 254-259.
    • (2000) Proceedings of the International Conference on Computer Aided Design , pp. 254-259
    • Dutt, S.1
  • 28
    • 0034855935 scopus 로고    scopus 로고
    • TCG: A transitive closure graph based representation for non-slicing floorplans
    • Las Vegas, NV
    • LIN, J. AND CHANG, Y. 2001. TCG: A transitive closure graph based representation for non-slicing floorplans. In Proceedings of the Design Automation Conference (Las Vegas, NV). 764-769.
    • (2001) Proceedings of the Design Automation Conference , pp. 764-769
    • Lin, J.1    Chang, Y.2
  • 30
    • 0030378255 scopus 로고    scopus 로고
    • VLSI module placement based on rectangle-packing by the sequence pair
    • MURATA, H., FUJIYOSHI, K., NAKATAKE, S., AND KAJITANI, Y. 1996. VLSI module placement based on rectangle-packing by the sequence pair. IEEE Trans. Comput.-Aided Des. 15, 12, 1518-1524.
    • (1996) IEEE Trans. Comput.-Aided Des. , vol.15 , Issue.12 , pp. 1518-1524
    • Murata, H.1    Fujiyoshi, K.2    Nakatake, S.3    Kajitani, Y.4
  • 32
    • 0006685403 scopus 로고    scopus 로고
    • Post-placement residual-overlap removal with minimal movement
    • Munich, Germany
    • NAG, S. AND CHAUDHARY, K. 1999. Post-placement residual-overlap removal with minimal movement. In Proceedings of the DATE (Munich, Germany). 581-586.
    • (1999) Proceedings of the DATE , pp. 581-586
    • Nag, S.1    Chaudhary, K.2
  • 36
    • 0002701738 scopus 로고    scopus 로고
    • Fast evaluation of sequence pair in block placement by longest common subsequence computation
    • Paris, France
    • TANG, X., TIAN, R., AND WONG, D. F. 2000. Fast evaluation of sequence pair in block placement by longest common subsequence computation. In Proceedings of the DATE (Paris, France). 106-111.
    • (2000) Proceedings of the DATE , pp. 106-111
    • Tang, X.1    Tian, R.2    Wong, D.F.3
  • 37
    • 84949784966 scopus 로고    scopus 로고
    • FAST-SP: A fast algorithm for block placement based on sequence pair
    • Yokohama, Japan
    • TANG, X. AND WONG, D. F. 2001. FAST-SP: A fast algorithm for block placement based on sequence pair. In Proceedings of the ASPDAC (Yokohama, Japan). 521-526.
    • (2001) Proceedings of the ASPDAC , pp. 521-526
    • Tang, X.1    Wong, D.F.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.