Solving modern mixed-size placement instances

Integration, the VLSI Journal

Volumn 42, Issue 2, 2009, Pages 262-275

  Roy, Jarrod A ^a   Ng, Aaron N ^b   Aggarwal, Rajat ^b   Ramachandran, Venky ^c   Markov, Igor L ^a  

^a The Department of Civil and Environmental Engineering   (United States)

^b XILINX INC   (United States)

^c Calypto Design Systems   (United States)

Author keywords

Circuit layout; Floorplanning; Placement; RTL

Indexed keywords

DIGITAL CIRCUITS; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS);

CIRCUIT LAYOUT; EMBEDDED MEMORIES; FLOORPLANNING; FUTURE TECHNOLOGIES; INTELLECTUAL PROPERTY BLOCKS; ON CHIPS; PHYSICAL DESIGNS; PLACEMENT; RTL; TRADITIONAL TECHNIQUES; WIRE LENGTHS;

DIGITAL INTEGRATED CIRCUITS;

EID: 58149112867     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2008.09.003     Document Type: Article

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