Robust mixed size placement under tight white space constraints

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 165-172

  Cong, Jason ^a   Romesis, Michail ^b   Shinnerl, Joseph R ^a  

^a University of California   (United States)

^b MAGMA DESIGN AUTOMATION   (United States)

Author keywords

Legalization; Mixed size placement; Recursive bipartitioning; Utilization; White space

Indexed keywords

LEGALIZATION; MIXED SIZE PLACEMENT; RECURSIVE BIPARTITIONING; RUN TIMES; WHITE SPACES;

ADAPTIVE ALGORITHMS; BENCHMARKING; FEEDBACK CONTROL; RECURSIVE FUNCTIONS; WIRE;

ROBUSTNESS (CONTROL SYSTEMS);

EID: 33748626715     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560058     Document Type: Conference Paper

References (30)

1. S. Adya, I. Markov, and P. Villarrubia. On whitespace and stability in mixed-size placement and physical synthesis. In Proc. Int'l Conf. on Computer-Aided Design, 2003.
2. S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and I. L. Markov. Unification of partitioning, placement, and floorplanning. In Proc. Int'l Conf. on Computer-Aided Design, pages 12-17, Nov. 2004.
3. S. N. Adya and I. L. Markov. Consistent placement of macro-blocks using floorplanning and standard-cell placement. In Proc. Int'l Symp. on Phys. Design, pages 12-17, April 2002.
4. U. Brenner and A. Rohe. An effective congestion-driven placement framework. TCAD, 22(4):387-394, April 2003.
5. A. Caldwell, A. Kahng, and I. Markov. Can recursive bisection produce routable placements? In Proc. 37th IEEE/ACM Design Automation Conf., pages 477-482, 2000.
6. T. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In Proc. Int'l Symp. on Phys. Design, pages 185-192, 2005.
7. C.-C. Chang, J. Cong, and X. Yuan. Multilevel placement for large-scale mixed-size ic designs. In Proc. Asia South Pacific Design Automation Conference, pages 325-330, 2003.
8. C. Chu and N. Viswanathan. FastPlace: Efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. In Proc. Int'l Symp. on Phys. Design, pages 26-33, April 2004.
9. J. Cong. An interconnect-centric design flow for nanometer technologies. Proceedings of the IEEE, 89(4):505-528, 2001.
10. J. Cong, M. Romesis, and J. Shinnerl. Fast floorplanning by look-ahead enabled recursive bipartitioning. In Asia South Pacific Design Automation Conf., 2005.
11. D. Hill. Method and system for high speed detailed placement of cells within an integrated circuit design. In US Patent 6370673, Apr 2002.
12. B. Hu and M. Marek-Sadowska. Fine granularity clustering based placement. TCAD, Apr. 2004.
13. A. Kahng and S. Reda. Placement feedback: A concept and method for better min-cut placements. In Proc. Design Automation Conf., pages 357-362, June 2004.
14. A. Kahng and Q. Wang. An analytic placer for mixed-size placement and timing-driven placement. In Proc. Int'l Conf. on Computer-Aided Design, pages 565-572, 2004.
15. A. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. In Proc. Int'l Symp. on Phys. Design, pages 18-25, 2004.
16. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Application in VLSI domain. In Proc. 34th ACM/IEEE Design Automation Conference, pages 526-529, 1997.
17. A. Khatkhate, C. Li, A. R. Agnihotri, S. Ono, M. C. Yildiz, C.-K. Koh, and P. H. Madden. Recursive bisection based mixed block placement. In Proc. Int'l Symp. on Phys. Design, 2004.
18. C. Li and C.-K. Koh. On improving recursive bipartitioning-based placement. Technical Report TR-ECE 03-14, Purdue University, 2003.
19. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. Rectangle-packing-based module placement. In Proc. International Conference on Computer-Aided Design, pages 472-479, 1995.
20. G. Nam, C. J. Alpert, P. Villarubia, B. Winter, and M. Yildiz. The ISPD2005 placement contest and benchmark suite. In Proc. Int'l Symp. on Phys. Design, pages 216-220, 2005.
21. P. N. Parakh, R. B. Brown, and K. A. Sakallah. Congestion driven quadratic placement. In Proc. Design Automation Conf., pages 275-278, 1998.
22. A. Ranjan, K. Bazargan, S. Ogrenci, and M. Sarrafzadeh. Fast floorplanning for effective prediction and construction. In IEEE Trans. on VLSI Sys., pages 341-351, 2001.
23. M. Sarrafzadeh, M. Wang, and X. Yang. Modern Placement Techiques. Kluwer, Boston, 2002.
24. P. Villarrubia, G. Nusbaum, R. Masleid, and E. Patel. IBM RISC chip design methodology. In ICCD, pages 143-147, 1989.
25. http://vlsicad.eecs.umich.edu/bk/pdtools/tar.gz/.
26. http://er.ce.ucla.edu/Dragon/
27. http://www.faraday-tech.com/structuredasic/download.html.
28. http://vlsicad.c8.binghamton.edu/software.html
29. Z. Xiu, J. Ma, S. Fowler, and R. Rutenbar. Large-scale placement by grid warping. In Proc. Design Automation Conf., pages 351-356, June 2004.
30. X. Yang, B. Choi, and M. Sarrafzadeh. Routability-driven white space allocation for fixed-die standard-cell placement. TCAD, 22(4):410-419, April 2003.